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llvm/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll 

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.b(<16 x i16>, <32 x i8>, <32 x i8>)

define <16 x i16> @lasx_xvmaddwev_h_b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_h_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.h.b $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmaddwev.w.h(<8 x i32>, <16 x i16>, <16 x i16>)

define <8 x i32> @lasx_xvmaddwev_w_h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_w_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.w.h $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmaddwev.w.h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwev.d.w(<4 x i64>, <8 x i32>, <8 x i32>)

define <4 x i64> @lasx_xvmaddwev_d_w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.d.w $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwev.d.w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwev.q.d(<4 x i64>, <4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmaddwev_q_d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_q_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.q.d $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwev.q.d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.bu(<16 x i16>, <32 x i8>, <32 x i8>)

define <16 x i16> @lasx_xvmaddwev_h_bu(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_h_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.h.bu $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.bu(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmaddwev.w.hu(<8 x i32>, <16 x i16>, <16 x i16>)

define <8 x i32> @lasx_xvmaddwev_w_hu(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_w_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.w.hu $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmaddwev.w.hu(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwev.d.wu(<4 x i64>, <8 x i32>, <8 x i32>)

define <4 x i64> @lasx_xvmaddwev_d_wu(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_d_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.d.wu $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwev.d.wu(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwev.q.du(<4 x i64>, <4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmaddwev_q_du(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_q_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.q.du $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwev.q.du(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.bu.b(<16 x i16>, <32 x i8>, <32 x i8>)

define <16 x i16> @lasx_xvmaddwev_h_bu_b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_h_bu_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.h.bu.b $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.bu.b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmaddwev.w.hu.h(<8 x i32>, <16 x i16>, <16 x i16>)

define <8 x i32> @lasx_xvmaddwev_w_hu_h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_w_hu_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.w.hu.h $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmaddwev.w.hu.h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwev.d.wu.w(<4 x i64>, <8 x i32>, <8 x i32>)

define <4 x i64> @lasx_xvmaddwev_d_wu_w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_d_wu_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.d.wu.w $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwev.d.wu.w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwev.q.du.d(<4 x i64>, <4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmaddwev_q_du_d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwev_q_du_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwev.q.du.d $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwev.q.du.d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmaddwod.h.b(<16 x i16>, <32 x i8>, <32 x i8>)

define <16 x i16> @lasx_xvmaddwod_h_b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_h_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.h.b $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmaddwod.h.b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmaddwod.w.h(<8 x i32>, <16 x i16>, <16 x i16>)

define <8 x i32> @lasx_xvmaddwod_w_h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_w_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.w.h $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmaddwod.w.h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwod.d.w(<4 x i64>, <8 x i32>, <8 x i32>)

define <4 x i64> @lasx_xvmaddwod_d_w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.d.w $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwod.d.w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwod.q.d(<4 x i64>, <4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmaddwod_q_d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_q_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.q.d $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwod.q.d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmaddwod.h.bu(<16 x i16>, <32 x i8>, <32 x i8>)

define <16 x i16> @lasx_xvmaddwod_h_bu(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_h_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.h.bu $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmaddwod.h.bu(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmaddwod.w.hu(<8 x i32>, <16 x i16>, <16 x i16>)

define <8 x i32> @lasx_xvmaddwod_w_hu(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_w_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.w.hu $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmaddwod.w.hu(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwod.d.wu(<4 x i64>, <8 x i32>, <8 x i32>)

define <4 x i64> @lasx_xvmaddwod_d_wu(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_d_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.d.wu $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwod.d.wu(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwod.q.du(<4 x i64>, <4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmaddwod_q_du(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_q_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.q.du $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwod.q.du(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmaddwod.h.bu.b(<16 x i16>, <32 x i8>, <32 x i8>)

define <16 x i16> @lasx_xvmaddwod_h_bu_b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_h_bu_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.h.bu.b $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmaddwod.h.bu.b(<16 x i16> %va, <32 x i8> %vb, <32 x i8> %vc)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmaddwod.w.hu.h(<8 x i32>, <16 x i16>, <16 x i16>)

define <8 x i32> @lasx_xvmaddwod_w_hu_h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_w_hu_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.w.hu.h $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmaddwod.w.hu.h(<8 x i32> %va, <16 x i16> %vb, <16 x i16> %vc)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwod.d.wu.w(<4 x i64>, <8 x i32>, <8 x i32>)

define <4 x i64> @lasx_xvmaddwod_d_wu_w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_d_wu_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.d.wu.w $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwod.d.wu.w(<4 x i64> %va, <8 x i32> %vb, <8 x i32> %vc)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmaddwod.q.du.d(<4 x i64>, <4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmaddwod_q_du_d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc) nounwind {
; CHECK-LABEL: lasx_xvmaddwod_q_du_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmaddwod.q.du.d $xr0, $xr1, $xr2
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmaddwod.q.du.d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc)
  ret <4 x i64> %res
}