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llvm/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll 

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8>)

define <16 x i16> @lasx_vext2xv_h_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_h_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.h.b $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8> %va)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.vext2xv.w.b(<32 x i8>)

define <8 x i32> @lasx_vext2xv_w_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_w_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.w.b $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.w.b(<32 x i8> %va)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.b(<32 x i8>)

define <4 x i64> @lasx_vext2xv_d_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_d_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.d.b $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.b(<32 x i8> %va)
  ret <4 x i64> %res
}

declare <8 x i32> @llvm.loongarch.lasx.vext2xv.w.h(<16 x i16>)

define <8 x i32> @lasx_vext2xv_w_h(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_w_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.w.h(<16 x i16> %va)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.h(<16 x i16>)

define <4 x i64> @lasx_vext2xv_d_h(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_d_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.d.h $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.h(<16 x i16> %va)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.w(<8 x i32>)

define <4 x i64> @lasx_vext2xv_d_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.w(<8 x i32> %va)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.vext2xv.hu.bu(<32 x i8>)

define <16 x i16> @lasx_vext2xv_hu_bu(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_hu_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.hu.bu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.vext2xv.hu.bu(<32 x i8> %va)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.bu(<32 x i8>)

define <8 x i32> @lasx_vext2xv_wu_bu(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_wu_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.wu.bu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.bu(<32 x i8> %va)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.bu(<32 x i8>)

define <4 x i64> @lasx_vext2xv_du_bu(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_du_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.du.bu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.bu(<32 x i8> %va)
  ret <4 x i64> %res
}

declare <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.hu(<16 x i16>)

define <8 x i32> @lasx_vext2xv_wu_hu(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_wu_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.wu.hu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.hu(<16 x i16> %va)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.hu(<16 x i16>)

define <4 x i64> @lasx_vext2xv_du_hu(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_du_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.du.hu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.hu(<16 x i16> %va)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.wu(<8 x i32>)

define <4 x i64> @lasx_vext2xv_du_wu(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_vext2xv_du_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vext2xv.du.wu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.wu(<8 x i32> %va)
  ret <4 x i64> %res
}