Codebase Browser
llvm
Go to App

llvm/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll 

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <32 x i8> @llvm.loongarch.lasx.xvmin.b(<32 x i8>, <32 x i8>)

define <32 x i8> @lasx_xvmin_b(<32 x i8> %va, <32 x i8> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.b $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <32 x i8> @llvm.loongarch.lasx.xvmin.b(<32 x i8> %va, <32 x i8> %vb)
  ret <32 x i8> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmin.h(<16 x i16>, <16 x i16>)

define <16 x i16> @lasx_xvmin_h(<16 x i16> %va, <16 x i16> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.h $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmin.h(<16 x i16> %va, <16 x i16> %vb)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmin.w(<8 x i32>, <8 x i32>)

define <8 x i32> @lasx_xvmin_w(<8 x i32> %va, <8 x i32> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.w $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmin.w(<8 x i32> %va, <8 x i32> %vb)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmin.d(<4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmin_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.d $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmin.d(<4 x i64> %va, <4 x i64> %vb)
  ret <4 x i64> %res
}

declare <32 x i8> @llvm.loongarch.lasx.xvmini.b(<32 x i8>, i32)

define <32 x i8> @lasx_xvmini_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.b $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <32 x i8> @llvm.loongarch.lasx.xvmini.b(<32 x i8> %va, i32 1)
  ret <32 x i8> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmini.h(<16 x i16>, i32)

define <16 x i16> @lasx_xvmini_h(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.h $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmini.h(<16 x i16> %va, i32 1)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmini.w(<8 x i32>, i32)

define <8 x i32> @lasx_xvmini_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.w $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmini.w(<8 x i32> %va, i32 1)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmini.d(<4 x i64>, i32)

define <4 x i64> @lasx_xvmini_d(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.d $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmini.d(<4 x i64> %va, i32 1)
  ret <4 x i64> %res
}

declare <32 x i8> @llvm.loongarch.lasx.xvmin.bu(<32 x i8>, <32 x i8>)

define <32 x i8> @lasx_xvmin_bu(<32 x i8> %va, <32 x i8> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.bu $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <32 x i8> @llvm.loongarch.lasx.xvmin.bu(<32 x i8> %va, <32 x i8> %vb)
  ret <32 x i8> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmin.hu(<16 x i16>, <16 x i16>)

define <16 x i16> @lasx_xvmin_hu(<16 x i16> %va, <16 x i16> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.hu $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmin.hu(<16 x i16> %va, <16 x i16> %vb)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmin.wu(<8 x i32>, <8 x i32>)

define <8 x i32> @lasx_xvmin_wu(<8 x i32> %va, <8 x i32> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.wu $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmin.wu(<8 x i32> %va, <8 x i32> %vb)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmin.du(<4 x i64>, <4 x i64>)

define <4 x i64> @lasx_xvmin_du(<4 x i64> %va, <4 x i64> %vb) nounwind {
; CHECK-LABEL: lasx_xvmin_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmin.du $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmin.du(<4 x i64> %va, <4 x i64> %vb)
  ret <4 x i64> %res
}

declare <32 x i8> @llvm.loongarch.lasx.xvmini.bu(<32 x i8>, i32)

define <32 x i8> @lasx_xvmini_bu(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.bu $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <32 x i8> @llvm.loongarch.lasx.xvmini.bu(<32 x i8> %va, i32 1)
  ret <32 x i8> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvmini.hu(<16 x i16>, i32)

define <16 x i16> @lasx_xvmini_hu(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.hu $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvmini.hu(<16 x i16> %va, i32 1)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvmini.wu(<8 x i32>, i32)

define <8 x i32> @lasx_xvmini_wu(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.wu $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvmini.wu(<8 x i32> %va, i32 1)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvmini.du(<4 x i64>, i32)

define <4 x i64> @lasx_xvmini_du(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvmini_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvmini.du $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvmini.du(<4 x i64> %va, i32 1)
  ret <4 x i64> %res
}