llvm/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfbfmin,+zvfbfmin,+v -target-abi ilp32d -verify-machineinstrs < %s \
; RUN:   | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfbfmin,+zvfbfmin,+v -target-abi lp64d -verify-machineinstrs < %s \
; RUN:   | FileCheck %s

define <vscale x 8 x bfloat> @vsplat_zero_nxv8f16() {
; CHECK-LABEL: vsplat_zero_nxv8f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    ret
  ret <vscale x 8 x bfloat> splat (bfloat zeroinitializer)
}

define <vscale x 8 x bfloat> @vsplat_negzero_nxv8f16() {
; CHECK-LABEL: vsplat_negzero_nxv8f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 1048568
; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT:    vmv.v.x v8, a0
; CHECK-NEXT:    ret
  ret <vscale x 8 x bfloat> splat (bfloat -0.0)
}