llvm/llvm/test/CodeGen/RISCV/rv64-typepromotion.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -mtriple=riscv64 -passes=typepromotion -S %s | FileCheck %s

; Test that this does not crash
define i16 @test(i8 %a, i32 %b) {
; CHECK-LABEL: define i16 @test(
; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[A]] to i32
; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[B]] to i16
; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[TMP1]] to i64
; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 0
; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 255
; CHECK-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT:    [[TMP6:%.*]] = xor i64 [[TMP5]], [[TMP2]]
; CHECK-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i16
; CHECK-NEXT:    ret i16 [[TMP7]]
;
entry:
  %0 = zext i8 %a to i32
  %1 = trunc i32 %b to i16
  %2 = icmp eq i16 %1, 0
  %3 = trunc i32 %0 to i8
  %4 = zext i8 %3 to i16
  %5 = xor i16 %4, %1
  ret i16 %5
}