llvm/llvm/test/CodeGen/RISCV/pr55201.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s

define i32 @f(i32 %x) {
; CHECK-LABEL: f:
; CHECK:       # %bb.0:
; CHECK-NEXT:    rori a0, a0, 27
; CHECK-NEXT:    ori a0, a0, 32
; CHECK-NEXT:    andi a0, a0, -31
; CHECK-NEXT:    ret
  %or1 = or i32 %x, 1
  %sh1 = shl i32 %or1, 5
  %sh2 = lshr i32 %x, 27
  %1 = and i32 %sh2, 1
  %r = or i32 %sh1, %1
  ret i32 %r
}