llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            sitofp_s16_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sitofp_s16_s32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:gprb(s32) = COPY $x10
    %1:fprb(s16) = G_SITOFP %0(s32)
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            uitofp_s16_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: uitofp_s16_s32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:gprb(s32) = COPY $x10
    %1:fprb(s16) = G_UITOFP %0(s32)
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...