llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64

---
name:            half_imm
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    ; RV32-LABEL: name: half_imm
    ; RV32: [[LUI:%[0-9]+]]:gpr = LUI 4
    ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 584
    ; RV32-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDI]]
    ; RV32-NEXT: $f10_h = COPY [[FMV_H_X]]
    ; RV32-NEXT: PseudoRET implicit $f10_h
    ;
    ; RV64-LABEL: name: half_imm
    ; RV64: [[LUI:%[0-9]+]]:gpr = LUI 4
    ; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 584
    ; RV64-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDIW]]
    ; RV64-NEXT: $f10_h = COPY [[FMV_H_X]]
    ; RV64-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = G_FCONSTANT half 0xH4248
    $f10_h = COPY %0(s16)
    PseudoRET implicit $f10_h

...
---
name:            half_imm_op
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $f10_h

    ; CHECK-LABEL: name: half_imm_op
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 15
    ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 10
    ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[SLLI]]
    ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[FMV_H_X]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FADD_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = G_FCONSTANT half 1.000000e+00
    %2:fprb(s16) = G_FADD %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            half_positive_zero
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: half_positive_zero
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
    ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[COPY]]
    ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %1:fprb(s16) = G_FCONSTANT half 0.000000e+00
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            half_negative_zero
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: half_negative_zero
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1048568
    ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[LUI]]
    ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %1:fprb(s16) = G_FCONSTANT half -0.000000e+00
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...