llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc-f16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            fpext_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h

    ; CHECK-LABEL: name: fpext_f32
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FCVT_S_H:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_H [[COPY]], 0
    ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s32) = G_FPEXT %0(s16)
    $f10_f = COPY %1(s32)
    PseudoRET implicit $f10_f

...
---
name:            fptrunc_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_f

    ; CHECK-LABEL: name: fptrunc_f32
    ; CHECK: liveins: $f10_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[FCVT_H_S:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_S [[COPY]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s16) = G_FPTRUNC %0(s32)
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            fpext_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h

    ; CHECK-LABEL: name: fpext_f64
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FCVT_D_H:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_H [[COPY]], 0
    ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_H]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s64) = G_FPEXT %0(s16)
    $f10_d = COPY %1(s64)
    PseudoRET implicit $f10_d

...
---
name:            fptrunc_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_d

    ; CHECK-LABEL: name: fptrunc_f64
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[FCVT_H_D:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_D [[COPY]], 7
    ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s16) = G_FPTRUNC %0(s64)
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...