llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
--- |
  define ptr @frame_index() {
  entry:
    %x = alloca i32, align 4
    ret ptr %x
  }

...
---
name:            frame_index
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gprb, preferred-register: '' }
stack:
  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body:             |
  bb.1.entry:
    ; CHECK-LABEL: name: frame_index
    ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
    $x10 = COPY %0(p0)
    PseudoRET implicit $x10

...