llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s

# On RISC-V, the MinStackArgumentAlignment is 1 and the ABI Alignment for p0 is
# greater than 1, so we will always generate code to adjust for this alignment.

---
name:            va_arg_i32
legalized:       false
tracksRegLiveness: true
fixedStack:
  - { id: 0, type: default, offset: 0, size: 4, alignment: 16,
      isImmutable: true, isAliased: false }
stack:
  - { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
machineFunctionInfo:
  varArgsFrameIndex: -1
  varArgsSaveSize: 0
body:             |
  bb.1:
    liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
    ; CHECK-LABEL: name: va_arg_i32
    ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4
    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0))
    ; CHECK-NEXT: PseudoRET
    %0:_(p0) = G_FRAME_INDEX %stack.0
    %1:_(s32) = G_VAARG %0(p0), 4
    PseudoRET
...
---
name:            va_arg_ptr
legalized:       false
tracksRegLiveness: true
fixedStack:
  - { id: 0, type: default, offset: 0, size: 4, alignment: 16,
      isImmutable: true, isAliased: false }
stack:
  - { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
machineFunctionInfo:
  varArgsFrameIndex: -1
  varArgsSaveSize: 0
body:             |
  bb.1:
    liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
    ; CHECK-LABEL: name: va_arg_ptr
    ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4
    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0))
    ; CHECK-NEXT: PseudoRET
    %0:_(p0) = G_FRAME_INDEX %stack.0
    %1:_(p0) = G_VAARG %0(p0), 4
    PseudoRET
...