legalize-vscale-rv32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s

---
name:            test_1_s32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_1_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = G_VSCALE i32 1
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_2_s32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_2_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = G_VSCALE i32 2
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_3_s32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_3_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = G_VSCALE i32 3
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_4_s32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_4_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = G_VSCALE i32 4
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_8_s32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_8_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = G_VSCALE i32 8
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_16_s32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_16_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = G_VSCALE i32 16
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_40_s32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_40_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[READ_VLENB]], [[C]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = G_VSCALE i32 40
    $x10 = COPY %0
    PseudoRET implicit $x10
...

---
name:            test_1_s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_1_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 1
    %1:_(s32) = G_TRUNC %0
    $x10 = COPY %1
    PseudoRET implicit $x10
...
---
name:            test_2_s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_2_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 2
    %1:_(s32) = G_TRUNC %0
    $x10 = COPY %1
    PseudoRET implicit $x10
...
---
name:            test_3_s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_3_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 3
    %1:_(s32) = G_TRUNC %0
    $x10 = COPY %1
    PseudoRET implicit $x10
...
---
name:            test_4_s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_4_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 4
    %1:_(s32) = G_TRUNC %0
    $x10 = COPY %1
    PseudoRET implicit $x10
...
---
name:            test_8_s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_8_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 8
    %1:_(s32) = G_TRUNC %0
    $x10 = COPY %1
    PseudoRET implicit $x10
...
---
name:            test_16_s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_16_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 16
    %1:_(s32) = G_TRUNC %0
    $x10 = COPY %1
    PseudoRET implicit $x10
...
---
name:            test_40_s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_40_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 40
    %1:_(s32) = G_TRUNC %0
    $x10 = COPY %1
    PseudoRET implicit $x10
...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
