llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s

---
name:            test_1
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_1
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 1
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_2
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_2
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 2
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_3
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_3
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 3
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_4
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_4
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 4
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_8
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_8
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
    ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 8
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_16
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_16
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[READ_VLENB]], [[C]](s64)
    ; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 16
    $x10 = COPY %0
    PseudoRET implicit $x10
...
---
name:            test_40
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: test_40
    ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[READ_VLENB]], [[C]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s64) = G_VSCALE i64 40
    $x10 = COPY %0
    PseudoRET implicit $x10
...