; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32 | FileCheck -check-prefix=RV32IZFINX %s
; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
; RUN: -target-abi=lp64 | FileCheck -check-prefix=RV64IZFINX %s
declare void @abort()
declare void @exit(i32)
declare float @dummy(float)
define void @br_fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_false:
; RV32IF: # %bb.0:
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: bnez a0, .LBB0_2
; RV32IF-NEXT: # %bb.1: # %if.then
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB0_2: # %if.else
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_false:
; RV64IF: # %bb.0:
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: bnez a0, .LBB0_2
; RV64IF-NEXT: # %bb.1: # %if.then
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB0_2: # %if.else
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_false:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: li a0, 1
; RV32IZFINX-NEXT: bnez a0, .LBB0_2
; RV32IZFINX-NEXT: # %bb.1: # %if.then
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB0_2: # %if.else
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_false:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: li a0, 1
; RV64IZFINX-NEXT: bnez a0, .LBB0_2
; RV64IZFINX-NEXT: # %bb.1: # %if.then
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB0_2: # %if.else
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp false float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
ret void
if.else:
tail call void @abort()
unreachable
}
define void @br_fcmp_oeq(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_oeq:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa1
; RV32IF-NEXT: bnez a0, .LBB1_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB1_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_oeq:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa1
; RV64IF-NEXT: bnez a0, .LBB1_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB1_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_oeq:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: feq.s a0, a0, a1
; RV32IZFINX-NEXT: bnez a0, .LBB1_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB1_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_oeq:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: feq.s a0, a0, a1
; RV64IZFINX-NEXT: bnez a0, .LBB1_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB1_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
; TODO: generated code quality for this is very poor due to
; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
; expansion.
define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_oeq_alt:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa1
; RV32IF-NEXT: bnez a0, .LBB2_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB2_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_oeq_alt:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa1
; RV64IF-NEXT: bnez a0, .LBB2_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB2_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_oeq_alt:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: feq.s a0, a0, a1
; RV32IZFINX-NEXT: bnez a0, .LBB2_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB2_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_oeq_alt:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: feq.s a0, a0, a1
; RV64IZFINX-NEXT: bnez a0, .LBB2_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB2_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
tail call void @abort()
unreachable
if.else:
ret void
}
define void @br_fcmp_ogt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ogt:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa1, fa0
; RV32IF-NEXT: bnez a0, .LBB3_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB3_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_ogt:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa1, fa0
; RV64IF-NEXT: bnez a0, .LBB3_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB3_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_ogt:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: flt.s a0, a1, a0
; RV32IZFINX-NEXT: bnez a0, .LBB3_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB3_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_ogt:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: flt.s a0, a1, a0
; RV64IZFINX-NEXT: bnez a0, .LBB3_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB3_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_oge(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_oge:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa1, fa0
; RV32IF-NEXT: bnez a0, .LBB4_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_oge:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa1, fa0
; RV64IF-NEXT: bnez a0, .LBB4_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB4_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_oge:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: fle.s a0, a1, a0
; RV32IZFINX-NEXT: bnez a0, .LBB4_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB4_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_oge:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: fle.s a0, a1, a0
; RV64IZFINX-NEXT: bnez a0, .LBB4_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB4_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_olt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_olt:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: bnez a0, .LBB5_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB5_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_olt:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: bnez a0, .LBB5_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB5_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_olt:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: flt.s a0, a0, a1
; RV32IZFINX-NEXT: bnez a0, .LBB5_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB5_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_olt:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: flt.s a0, a0, a1
; RV64IZFINX-NEXT: bnez a0, .LBB5_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB5_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_ole(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ole:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa0, fa1
; RV32IF-NEXT: bnez a0, .LBB6_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB6_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_ole:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa0, fa1
; RV64IF-NEXT: bnez a0, .LBB6_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB6_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_ole:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: fle.s a0, a0, a1
; RV32IZFINX-NEXT: bnez a0, .LBB6_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB6_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_ole:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: fle.s a0, a0, a1
; RV64IZFINX-NEXT: bnez a0, .LBB6_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB6_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_one(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_one:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: flt.s a1, fa1, fa0
; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB7_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB7_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_one:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: flt.s a1, fa1, fa0
; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB7_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB7_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_one:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: flt.s a2, a0, a1
; RV32IZFINX-NEXT: flt.s a0, a1, a0
; RV32IZFINX-NEXT: or a0, a0, a2
; RV32IZFINX-NEXT: bnez a0, .LBB7_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB7_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_one:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: flt.s a2, a0, a1
; RV64IZFINX-NEXT: flt.s a0, a1, a0
; RV64IZFINX-NEXT: or a0, a0, a2
; RV64IZFINX-NEXT: bnez a0, .LBB7_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB7_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_ord(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ord:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa1, fa1
; RV32IF-NEXT: feq.s a1, fa0, fa0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB8_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_ord:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa1, fa1
; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB8_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_ord:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: feq.s a1, a1, a1
; RV32IZFINX-NEXT: feq.s a0, a0, a0
; RV32IZFINX-NEXT: and a0, a0, a1
; RV32IZFINX-NEXT: bnez a0, .LBB8_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB8_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_ord:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: feq.s a1, a1, a1
; RV64IZFINX-NEXT: feq.s a0, a0, a0
; RV64IZFINX-NEXT: and a0, a0, a1
; RV64IZFINX-NEXT: bnez a0, .LBB8_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB8_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ueq:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: flt.s a1, fa1, fa0
; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: beqz a0, .LBB9_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB9_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_ueq:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: flt.s a1, fa1, fa0
; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: beqz a0, .LBB9_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB9_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_ueq:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: flt.s a2, a0, a1
; RV32IZFINX-NEXT: flt.s a0, a1, a0
; RV32IZFINX-NEXT: or a0, a0, a2
; RV32IZFINX-NEXT: beqz a0, .LBB9_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB9_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_ueq:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: flt.s a2, a0, a1
; RV64IZFINX-NEXT: flt.s a0, a1, a0
; RV64IZFINX-NEXT: or a0, a0, a2
; RV64IZFINX-NEXT: beqz a0, .LBB9_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB9_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_ugt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ugt:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa0, fa1
; RV32IF-NEXT: beqz a0, .LBB10_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB10_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_ugt:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa0, fa1
; RV64IF-NEXT: beqz a0, .LBB10_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB10_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_ugt:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: fle.s a0, a0, a1
; RV32IZFINX-NEXT: beqz a0, .LBB10_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB10_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_ugt:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: fle.s a0, a0, a1
; RV64IZFINX-NEXT: beqz a0, .LBB10_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB10_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_uge(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_uge:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: beqz a0, .LBB11_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB11_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_uge:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: beqz a0, .LBB11_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB11_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_uge:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: flt.s a0, a0, a1
; RV32IZFINX-NEXT: beqz a0, .LBB11_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB11_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_uge:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: flt.s a0, a0, a1
; RV64IZFINX-NEXT: beqz a0, .LBB11_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB11_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_ult(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ult:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa1, fa0
; RV32IF-NEXT: beqz a0, .LBB12_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB12_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_ult:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa1, fa0
; RV64IF-NEXT: beqz a0, .LBB12_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB12_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_ult:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: fle.s a0, a1, a0
; RV32IZFINX-NEXT: beqz a0, .LBB12_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB12_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_ult:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: fle.s a0, a1, a0
; RV64IZFINX-NEXT: beqz a0, .LBB12_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB12_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_ule(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ule:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa1, fa0
; RV32IF-NEXT: beqz a0, .LBB13_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB13_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_ule:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa1, fa0
; RV64IF-NEXT: beqz a0, .LBB13_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB13_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_ule:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: flt.s a0, a1, a0
; RV32IZFINX-NEXT: beqz a0, .LBB13_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB13_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_ule:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: flt.s a0, a1, a0
; RV64IZFINX-NEXT: beqz a0, .LBB13_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB13_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_une(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_une:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa1
; RV32IF-NEXT: beqz a0, .LBB14_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB14_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_une:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa1
; RV64IF-NEXT: beqz a0, .LBB14_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB14_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_une:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: feq.s a0, a0, a1
; RV32IZFINX-NEXT: beqz a0, .LBB14_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB14_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_une:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: feq.s a0, a0, a1
; RV64IZFINX-NEXT: beqz a0, .LBB14_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB14_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_uno(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_uno:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa1, fa1
; RV32IF-NEXT: feq.s a1, fa0, fa0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: beqz a0, .LBB15_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB15_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_uno:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa1, fa1
; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: beqz a0, .LBB15_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB15_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_uno:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: feq.s a1, a1, a1
; RV32IZFINX-NEXT: feq.s a0, a0, a0
; RV32IZFINX-NEXT: and a0, a0, a1
; RV32IZFINX-NEXT: beqz a0, .LBB15_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB15_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_uno:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: feq.s a1, a1, a1
; RV64IZFINX-NEXT: feq.s a0, a0, a0
; RV64IZFINX-NEXT: and a0, a0, a1
; RV64IZFINX-NEXT: beqz a0, .LBB15_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB15_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
define void @br_fcmp_true(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_true:
; RV32IF: # %bb.0:
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: bnez a0, .LBB16_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB16_2: # %if.then
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_true:
; RV64IF: # %bb.0:
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: bnez a0, .LBB16_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB16_2: # %if.then
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_true:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: li a0, 1
; RV32IZFINX-NEXT: bnez a0, .LBB16_2
; RV32IZFINX-NEXT: # %bb.1: # %if.else
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB16_2: # %if.then
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_true:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: li a0, 1
; RV64IZFINX-NEXT: bnez a0, .LBB16_2
; RV64IZFINX-NEXT: # %bb.1: # %if.else
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB16_2: # %if.then
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: call abort
%1 = fcmp true float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
ret void
if.then:
tail call void @abort()
unreachable
}
; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot
; and RISCVInstrInfo::loadRegFromStackSlot
define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
; RV32IF: # %bb.0: # %entry
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x fs0, zero
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call dummy
; RV32IF-NEXT: feq.s a0, fa0, fs0
; RV32IF-NEXT: beqz a0, .LBB17_3
; RV32IF-NEXT: # %bb.1: # %if.end
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call dummy
; RV32IF-NEXT: feq.s a0, fa0, fs0
; RV32IF-NEXT: beqz a0, .LBB17_3
; RV32IF-NEXT: # %bb.2: # %if.end4
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB17_3: # %if.then
; RV32IF-NEXT: call abort
;
; RV64IF-LABEL: br_fcmp_store_load_stack_slot:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.w.x fs0, zero
; RV64IF-NEXT: fmv.s fa0, fs0
; RV64IF-NEXT: call dummy
; RV64IF-NEXT: feq.s a0, fa0, fs0
; RV64IF-NEXT: beqz a0, .LBB17_3
; RV64IF-NEXT: # %bb.1: # %if.end
; RV64IF-NEXT: fmv.s fa0, fs0
; RV64IF-NEXT: call dummy
; RV64IF-NEXT: feq.s a0, fa0, fs0
; RV64IF-NEXT: beqz a0, .LBB17_3
; RV64IF-NEXT: # %bb.2: # %if.end4
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB17_3: # %if.then
; RV64IF-NEXT: call abort
;
; RV32IZFINX-LABEL: br_fcmp_store_load_stack_slot:
; RV32IZFINX: # %bb.0: # %entry
; RV32IZFINX-NEXT: addi sp, sp, -16
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINX-NEXT: li a0, 0
; RV32IZFINX-NEXT: call dummy
; RV32IZFINX-NEXT: feq.s a0, a0, zero
; RV32IZFINX-NEXT: beqz a0, .LBB17_3
; RV32IZFINX-NEXT: # %bb.1: # %if.end
; RV32IZFINX-NEXT: li a0, 0
; RV32IZFINX-NEXT: call dummy
; RV32IZFINX-NEXT: feq.s a0, a0, zero
; RV32IZFINX-NEXT: beqz a0, .LBB17_3
; RV32IZFINX-NEXT: # %bb.2: # %if.end4
; RV32IZFINX-NEXT: li a0, 0
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: ret
; RV32IZFINX-NEXT: .LBB17_3: # %if.then
; RV32IZFINX-NEXT: call abort
;
; RV64IZFINX-LABEL: br_fcmp_store_load_stack_slot:
; RV64IZFINX: # %bb.0: # %entry
; RV64IZFINX-NEXT: addi sp, sp, -16
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINX-NEXT: li a0, 0
; RV64IZFINX-NEXT: call dummy
; RV64IZFINX-NEXT: feq.s a0, a0, zero
; RV64IZFINX-NEXT: beqz a0, .LBB17_3
; RV64IZFINX-NEXT: # %bb.1: # %if.end
; RV64IZFINX-NEXT: li a0, 0
; RV64IZFINX-NEXT: call dummy
; RV64IZFINX-NEXT: feq.s a0, a0, zero
; RV64IZFINX-NEXT: beqz a0, .LBB17_3
; RV64IZFINX-NEXT: # %bb.2: # %if.end4
; RV64IZFINX-NEXT: li a0, 0
; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINX-NEXT: addi sp, sp, 16
; RV64IZFINX-NEXT: ret
; RV64IZFINX-NEXT: .LBB17_3: # %if.then
; RV64IZFINX-NEXT: call abort
entry:
%call = call float @dummy(float 0.000000e+00)
%cmp = fcmp une float %call, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end
if.then:
call void @abort()
unreachable
if.end:
%call1 = call float @dummy(float 0.000000e+00)
%cmp2 = fcmp une float %call1, 0.000000e+00
br i1 %cmp2, label %if.then3, label %if.end4
if.then3:
call void @abort()
unreachable
if.end4:
ret i32 0
}
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