llvm/llvm/test/CodeGen/X86/vshift_split.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s

; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
; CHECK-LABEL: update:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movdqa %xmm0, %xmm1
; CHECK-NEXT:    psrlq $2, %xmm1
; CHECK-NEXT:    psrlq $3, %xmm0
; CHECK-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; CHECK-NEXT:    retl
entry:
	%shr = lshr <2 x i64> %val, < i64 2, i64 3 >
	ret <2 x i64> %shr
}