# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s
# GFX12: s_addk_co_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
0x34,0x12,0xff,0xb7
# GFX12: s_addk_co_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0xfe,0xb7]
0x34,0x12,0xfe,0xb7
# GFX12: s_addk_co_i32 m0, 0x1234 ; encoding: [0x34,0x12,0xfd,0xb7]
0x34,0x12,0xfd,0xb7
# GFX12: s_addk_co_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x80,0xb7]
0x34,0x12,0x80,0xb7
# GFX12: s_addk_co_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x80,0xb7]
0xd1,0xc1,0x80,0xb7
# GFX12: s_addk_co_i32 s105, 0x1234 ; encoding: [0x34,0x12,0xe9,0xb7]
0x34,0x12,0xe9,0xb7
# GFX12: s_addk_co_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0xeb,0xb7]
0x34,0x12,0xeb,0xb7
# GFX12: s_addk_co_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0xea,0xb7]
0x34,0x12,0xea,0xb7
# GFX12: s_call_b64 exec, 4660 ; encoding: [0x34,0x12,0x7e,0xba]
0x34,0x12,0x7e,0xba
# GFX12: s_call_b64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xba]
0x34,0x12,0x00,0xba
# GFX12: s_call_b64 s[104:105], 4660 ; encoding: [0x34,0x12,0x68,0xba]
0x34,0x12,0x68,0xba
# GFX12: s_call_b64 vcc, 4660 ; encoding: [0x34,0x12,0x6a,0xba]
0x34,0x12,0x6a,0xba
# GFX12: s_call_b64 null, 4660 ; encoding: [0x34,0x12,0x7c,0xba]
0x34,0x12,0x7c,0xba
# GFX12: s_cmovk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb1]
0x34,0x12,0x7f,0xb1
# GFX12: s_cmovk_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0x7e,0xb1]
0x34,0x12,0x7e,0xb1
# GFX12: s_cmovk_i32 m0, 0x1234 ; encoding: [0x34,0x12,0x7d,0xb1]
0x34,0x12,0x7d,0xb1
# GFX12: s_cmovk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb1]
0x34,0x12,0x00,0xb1
# GFX12: s_cmovk_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x00,0xb1]
0xd1,0xc1,0x00,0xb1
# GFX12: s_cmovk_i32 s105, 0x1234 ; encoding: [0x34,0x12,0x69,0xb1]
0x34,0x12,0x69,0xb1
# GFX12: s_cmovk_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0x6b,0xb1]
0x34,0x12,0x6b,0xb1
# GFX12: s_cmovk_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0x6a,0xb1]
0x34,0x12,0x6a,0xb1
# GFX12: s_getreg_b32 exec_hi, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xff,0xb8]
0x34,0x12,0xff,0xb8
# GFX12: s_getreg_b32 exec_lo, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xfe,0xb8]
0x34,0x12,0xfe,0xb8
# GFX12: s_getreg_b32 m0, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xfd,0xb8]
0x34,0x12,0xfd,0xb8
# GFX12: s_getreg_b32 s0, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0x80,0xb8]
0x34,0x12,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV, 7, 25) ; encoding: [0xd1,0xc1,0x80,0xb8]
0xd1,0xc1,0x80,0xb8
# GFX12: s_getreg_b32 s105, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xe9,0xb8]
0x34,0x12,0xe9,0xb8
# GFX12: s_getreg_b32 vcc_hi, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xeb,0xb8]
0x34,0x12,0xeb,0xb8
# GFX12: s_getreg_b32 vcc_lo, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xea,0xb8]
0x34,0x12,0xea,0xb8
# GFX12: s_movk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb0]
0x34,0x12,0x7f,0xb0
# GFX12: s_movk_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0x7e,0xb0]
0x34,0x12,0x7e,0xb0
# GFX12: s_movk_i32 m0, 0x1234 ; encoding: [0x34,0x12,0x7d,0xb0]
0x34,0x12,0x7d,0xb0
# GFX12: s_movk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb0]
0x34,0x12,0x00,0xb0
# GFX12: s_movk_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x00,0xb0]
0xd1,0xc1,0x00,0xb0
# GFX12: s_movk_i32 s105, 0x1234 ; encoding: [0x34,0x12,0x69,0xb0]
0x34,0x12,0x69,0xb0
# GFX12: s_movk_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0x6b,0xb0]
0x34,0x12,0x6b,0xb0
# GFX12: s_movk_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0x6a,0xb0]
0x34,0x12,0x6a,0xb0
# GFX12: s_mulk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb8]
0x34,0x12,0x7f,0xb8
# GFX12: s_mulk_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0x7e,0xb8]
0x34,0x12,0x7e,0xb8
# GFX12: s_mulk_i32 m0, 0x1234 ; encoding: [0x34,0x12,0x7d,0xb8]
0x34,0x12,0x7d,0xb8
# GFX12: s_mulk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb8]
0x34,0x12,0x00,0xb8
# GFX12: s_mulk_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x00,0xb8]
0xd1,0xc1,0x00,0xb8
# GFX12: s_mulk_i32 s105, 0x1234 ; encoding: [0x34,0x12,0x69,0xb8]
0x34,0x12,0x69,0xb8
# GFX12: s_mulk_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0x6b,0xb8]
0x34,0x12,0x6b,0xb8
# GFX12: s_mulk_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0x6a,0xb8]
0x34,0x12,0x6a,0xb8
# GFX12: s_setreg_b32 hwreg(52, 8, 3), exec_hi ; encoding: [0x34,0x12,0x7f,0xb9]
0x34,0x12,0x7f,0xb9
# GFX12: s_setreg_b32 hwreg(52, 8, 3), exec_lo ; encoding: [0x34,0x12,0x7e,0xb9]
0x34,0x12,0x7e,0xb9
# GFX12: s_setreg_b32 hwreg(52, 8, 3), m0 ; encoding: [0x34,0x12,0x7d,0xb9]
0x34,0x12,0x7d,0xb9
# GFX12: s_setreg_b32 hwreg(52, 8, 3), s0 ; encoding: [0x34,0x12,0x00,0xb9]
0x34,0x12,0x00,0xb9
# GFX12: s_setreg_b32 hwreg(52, 8, 3), s105 ; encoding: [0x34,0x12,0x69,0xb9]
0x34,0x12,0x69,0xb9
# GFX12: s_setreg_b32 hwreg(52, 8, 3), vcc_hi ; encoding: [0x34,0x12,0x6b,0xb9]
0x34,0x12,0x6b,0xb9
# GFX12: s_setreg_b32 hwreg(52, 8, 3), vcc_lo ; encoding: [0x34,0x12,0x6a,0xb9]
0x34,0x12,0x6a,0xb9
# GFX12: s_setreg_b32 hwreg(HW_REG_EXCP_FLAG_PRIV, 7, 25), s0 ; encoding: [0xd1,0xc1,0x00,0xb9]
0xd1,0xc1,0x00,0xb9
# GFX12: s_version 0x1234 ; encoding: [0x34,0x12,0x80,0xb0]
0x34,0x12,0x80,0xb0
# GFX12: s_version 0xc1d1 ; encoding: [0xd1,0xc1,0x80,0xb0]
0xd1,0xc1,0x80,0xb0
# GFX12: s_version UC_VERSION_GFX12 ; encoding: [0x09,0x00,0x80,0xb0]
0x09,0x00,0x80,0xb0
# GFX12: s_version UC_VERSION_GFX12|UC_VERSION_W32_BIT ; encoding: [0x09,0x40,0x80,0xb0]
0x09,0x40,0x80,0xb0
# GFX12: s_version UC_VERSION_GFX12|UC_VERSION_W64_BIT ; encoding: [0x09,0x20,0x80,0xb0]
0x09,0x20,0x80,0xb0
# GFX12: s_version UC_VERSION_GFX12|UC_VERSION_MDP_BIT ; encoding: [0x09,0x80,0x80,0xb0]
0x09,0x80,0x80,0xb0
# GFX12: s_version ((128|UC_VERSION_W64_BIT)|UC_VERSION_W32_BIT)|UC_VERSION_MDP_BIT ; encoding: [0x80,0xe0,0x80,0xb0]
0x80,0xe0,0x80,0xb0
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_MODE), 0xaf123456 ; encoding: [0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 31, 1), 0xaf123456 ; encoding: [0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf]
0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_STATUS), 0xaf123456 ; encoding: [0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC), 0xaf123456 ; encoding: [0x05,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x05,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC), 0xaf123456 ; encoding: [0x06,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x06,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0xaf123456 ; encoding: [0x07,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x07,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID1), 0xaf123456 ; encoding: [0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID2), 0xaf123456 ; encoding: [0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_MODE) ; encoding: [0x01,0xf8,0x80,0xb8]
0x01,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_STATUS) ; encoding: [0x02,0xf8,0x80,0xb8]
0x02,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_STATE_PRIV) ; encoding: [0x04,0xf8,0x80,0xb8]
0x04,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_GPR_ALLOC) ; encoding: [0x05,0xf8,0x80,0xb8]
0x05,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x80,0xb8]
0x06,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_IB_STS) ; encoding: [0x07,0xf8,0x80,0xb8]
0x07,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA) ; encoding: [0x0a,0xf8,0x80,0xb8]
0x0a,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) ; encoding: [0x0b,0xf8,0x80,0xb8]
0x0b,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) ; encoding: [0x0c,0xf8,0x80,0xb8]
0x0c,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA1) ; encoding: [0x0f,0xf8,0x80,0xb8]
0x0f,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA2) ; encoding: [0x10,0xf8,0x80,0xb8]
0x10,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV) ; encoding: [0x11,0xf8,0x80,0xb8]
0x11,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_USER) ; encoding: [0x12,0xf8,0x80,0xb8]
0x12,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_TRAP_CTRL) ; encoding: [0x13,0xf8,0x80,0xb8]
0x13,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_LO) ; encoding: [0x14,0xf8,0x80,0xb8]
0x14,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_HI) ; encoding: [0x15,0xf8,0x80,0xb8]
0x15,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_HW_ID1) ; encoding: [0x17,0xf8,0x80,0xb8]
0x17,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_HW_ID2) ; encoding: [0x18,0xf8,0x80,0xb8]
0x18,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_LO) ; encoding: [0x1f,0xf8,0x80,0xb8]
0x1f,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_HI) ; encoding: [0x20,0xf8,0x80,0xb8]
0x20,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_LO) ; encoding: [0x1d,0xf8,0x80,0xb8]
0x1d,0xf8,0x80,0xb8
# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_HI) ; encoding: [0x1e,0xf8,0x80,0xb8]
0x1e,0xf8,0x80,0xb8
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