llvm/llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt

# RUN: llvm-mc -triple=aarch64 -mattr +gcs -disassemble %s 2> %t | FileCheck %s

[0x00,0x25,0x18,0xd5]
[0x01,0x25,0x38,0xd5]
// CHECK: msr     GCSCR_EL1, x0
// CHECK: mrs     x1, GCSCR_EL1

[0x22,0x25,0x18,0xd5]
[0x23,0x25,0x38,0xd5]
// CHECK: msr     GCSPR_EL1, x2
// CHECK: mrs     x3, GCSPR_EL1

[0x44,0x25,0x18,0xd5]
[0x45,0x25,0x38,0xd5]
// CHECK: msr     GCSCRE0_EL1, x4
// CHECK: mrs     x5, GCSCRE0_EL1

[0x26,0x25,0x1b,0xd5]
[0x27,0x25,0x3b,0xd5]
// CHECK: msr     GCSPR_EL0, x6
// CHECK: mrs     x7, GCSPR_EL0

[0x0a,0x25,0x1c,0xd5]
[0x0b,0x25,0x3c,0xd5]
// CHECK: msr     GCSCR_EL2, x10
// CHECK: mrs     x11, GCSCR_EL2

[0x2c,0x25,0x1c,0xd5]
[0x2d,0x25,0x3c,0xd5]
// CHECK: msr     GCSPR_EL2, x12
// CHECK: mrs     x13, GCSPR_EL2

[0x0e,0x25,0x1d,0xd5]
[0x0f,0x25,0x3d,0xd5]
// CHECK: msr     GCSCR_EL12, x14
// CHECK: mrs     x15, GCSCR_EL12

[0x30,0x25,0x1d,0xd5]
[0x31,0x25,0x3d,0xd5]
// CHECK: msr     GCSPR_EL12, x16
// CHECK: mrs     x17, GCSPR_EL12

[0x12,0x25,0x1e,0xd5]
[0x13,0x25,0x3e,0xd5]
// CHECK: msr     GCSCR_EL3, x18
// CHECK: mrs     x19, GCSCR_EL3

[0x34,0x25,0x1e,0xd5]
[0x35,0x25,0x3e,0xd5]
// CHECK: msr     GCSPR_EL3, x20
// CHECK: mrs     x21, GCSPR_EL3

[0x55,0x77,0x0b,0xd5]
// CHECK: gcsss1 x21

[0x76,0x77,0x2b,0xd5]
// CHECK: gcsss2    x22

[0x19,0x77,0x0b,0xd5]
// CHECK: gcspushm x25

[0x3f,0x77,0x2b,0xd5]
// CHECK: gcspopm

[0x39,0x77,0x2b,0xd5]
// CHECK: gcspopm    x25

[0x7f,0x22,0x03,0xd5]
// CHECK: gcsb    dsync

[0x7a,0x0f,0x1f,0xd9]
// CHECK: gcsstr   x26, [x27]

[0xfa,0x0f,0x1f,0xd9]
// CHECK: gcsstr   x26, [sp]

[0x7a,0x1f,0x1f,0xd9]
// CHECK: gcssttr  x26, [x27]

[0xfa,0x1f,0x1f,0xd9]
// CHECK: gcssttr  x26, [sp]

[0x9f,0x77,0x08,0xd5]
// CHECK: gcspushx

[0xbf,0x77,0x08,0xd5]
// CHECK: gcspopcx

[0xdf,0x77,0x08,0xd5]
// CHECK: gcspopx