llvm/polly/test/CodeGen/MemAccess/codegen_simple_md___%for.cond---%for.end6.jscop.transformed+withoutconst

{
   "context" : "{  :  }",
   "name" : "for.cond => for.end6",
   "statements" : [
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "{ Stmt_for_body3[i0, i1] -> MemRef_A[16i0 + 2i1] }"
            }
         ],
         "domain" : "{ Stmt_for_body3[i0, i1] : i0 >= 0 and i0 <= 31 and i1 >= 0 and i1 <= 31 }",
         "name" : "Stmt_for_body3",
         "schedule" : "{ Stmt_for_body3[i0, i1] -> [0, i0, 0, i1, 0] }"
      }
   ]
}