llvm/polly/test/CodeGen/MemAccess/simple___%for.cond---%for.end14.jscop.transformed

{
   "context" : "{  :  }",
   "name" : "for.cond => for.end14",
   "statements" : [
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "{ Stmt_for_body[i0] -> MemRef_A[0] }"
            }
         ],
         "domain" : "{ Stmt_for_body[i0] : i0 >= 0 and i0 <= 11 }",
         "name" : "Stmt_for_body",
         "schedule" : "{ Stmt_for_body[i0] -> [0, i0, 0] }"
      },
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "{ Stmt_for_body7[i0] -> MemRef_B[0] }"
            }
         ],
         "domain" : "{ Stmt_for_body7[i0] : i0 >= 0 and i0 <= 11 }",
         "name" : "Stmt_for_body7",
         "schedule" : "{ Stmt_for_body7[i0] -> [0, i0, 0] }"
      }
   ]
}