llvm/lld/ELF/Arch/Hexagon.cpp

//===-- Hexagon.cpp -------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "InputFiles.h"
#include "Symbols.h"
#include "SyntheticSections.h"
#include "Target.h"
#include "lld/Common/ErrorHandler.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/Support/Endian.h"

usingnamespacellvm;
usingnamespacellvm::object;
usingnamespacellvm::support::endian;
usingnamespacellvm::ELF;
usingnamespacelld;
usingnamespacelld::elf;

namespace {
class Hexagon final : public TargetInfo {};
} // namespace

Hexagon::Hexagon() {}

uint32_t Hexagon::calcEFlags() const {}

static uint32_t applyMask(uint32_t mask, uint32_t data) {}

RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
                            const uint8_t *loc) const {}

// There are (arguably too) many relocation masks for the DSP's
// R_HEX_6_X type.  The table below is used to select the correct mask
// for the given instruction.
struct InstructionMask {};
static const InstructionMask r6[] =;

static bool isDuplex(uint32_t insn) {}

static uint32_t findMaskR6(uint32_t insn) {}

static uint32_t findMaskR8(uint32_t insn) {}

static uint32_t findMaskR11(uint32_t insn) {}

static uint32_t findMaskR16(uint32_t insn) {}

static void or32le(uint8_t *p, int32_t v) {}

void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
                       uint64_t val) const {}

void Hexagon::writePltHeader(uint8_t *buf) const {}

void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
                       uint64_t pltEntryAddr) const {}

RelType Hexagon::getDynRel(RelType type) const {}

int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {}

TargetInfo *elf::getHexagonTargetInfo() {}