; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zfhmin,+zvfh,+zvfbfmin \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zfhmin,+zvfh,+zvfbfmin \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.iXLen(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
iXLen)
define <vscale x 1 x i8> @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.iXLen(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.iXLen(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i8> @intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.iXLen(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.iXLen(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
iXLen)
define <vscale x 2 x i8> @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.iXLen(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.iXLen(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i8> @intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.iXLen(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.iXLen(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
iXLen)
define <vscale x 4 x i8> @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.iXLen(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.iXLen(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i8> @intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.iXLen(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.iXLen(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen)
define <vscale x 8 x i8> @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.iXLen(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.iXLen(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i8> @intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.iXLen(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.iXLen(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
iXLen)
define <vscale x 16 x i8> @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.iXLen(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.iXLen(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x i8> @intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.iXLen(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.iXLen(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
iXLen)
define <vscale x 32 x i8> @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.iXLen(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.iXLen(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x i8> @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.iXLen(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.iXLen(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
iXLen)
define <vscale x 64 x i8> @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.iXLen(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
iXLen %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.iXLen(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
iXLen,
iXLen)
define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.iXLen(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.iXLen(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
iXLen)
define <vscale x 1 x i16> @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.iXLen(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.iXLen(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i16> @intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.iXLen(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.iXLen(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
iXLen)
define <vscale x 2 x i16> @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.iXLen(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.iXLen(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i16> @intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.iXLen(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.iXLen(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
iXLen)
define <vscale x 4 x i16> @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.iXLen(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.iXLen(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i16> @intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.iXLen(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.iXLen(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
iXLen)
define <vscale x 8 x i16> @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.iXLen(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.iXLen(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i16> @intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.iXLen(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.iXLen(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
iXLen)
define <vscale x 16 x i16> @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.iXLen(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.iXLen(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x i16> @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.iXLen(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.iXLen(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
iXLen)
define <vscale x 32 x i16> @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.iXLen(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
iXLen %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.iXLen(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.iXLen(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.iXLen(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
iXLen)
define <vscale x 1 x i32> @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.iXLen(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.iXLen(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i32> @intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.iXLen(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.iXLen(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
iXLen)
define <vscale x 2 x i32> @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.iXLen(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.iXLen(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i32> @intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.iXLen(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.iXLen(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
iXLen)
define <vscale x 4 x i32> @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.iXLen(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.iXLen(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i32> @intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.iXLen(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.iXLen(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
iXLen)
define <vscale x 8 x i32> @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.iXLen(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.iXLen(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i32> @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.iXLen(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.iXLen(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
iXLen)
define <vscale x 16 x i32> @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.iXLen(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
iXLen %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.iXLen(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.iXLen(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.iXLen(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
iXLen)
define <vscale x 1 x i64> @intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.iXLen(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
iXLen %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.iXLen(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i64> @intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.iXLen(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.iXLen(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
iXLen)
define <vscale x 2 x i64> @intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.iXLen(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
iXLen %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.iXLen(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i64> @intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.iXLen(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.iXLen(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
iXLen)
define <vscale x 4 x i64> @intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.iXLen(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
iXLen %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.iXLen(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i64> @intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.iXLen(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.iXLen(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
iXLen)
define <vscale x 8 x i64> @intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.iXLen(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
iXLen %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.iXLen(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i64> @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.iXLen(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.iXLen(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i16>,
iXLen)
define <vscale x 1 x half> @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.iXLen(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0,
<vscale x 1 x i16> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.mask.nxv1f16.iXLen(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x half> @intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.mask.nxv1f16.iXLen(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.iXLen(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i16>,
iXLen)
define <vscale x 2 x half> @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.iXLen(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0,
<vscale x 2 x i16> %1,
iXLen %2)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.mask.nxv2f16.iXLen(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x half> @intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.mask.nxv2f16.iXLen(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.iXLen(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i16>,
iXLen)
define <vscale x 4 x half> @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.iXLen(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0,
<vscale x 4 x i16> %1,
iXLen %2)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.mask.nxv4f16.iXLen(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x half> @intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.mask.nxv4f16.iXLen(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.iXLen(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i16>,
iXLen)
define <vscale x 8 x half> @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.iXLen(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0,
<vscale x 8 x i16> %1,
iXLen %2)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.mask.nxv8f16.iXLen(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x half> @intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.mask.nxv8f16.iXLen(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.iXLen(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i16>,
iXLen)
define <vscale x 16 x half> @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.iXLen(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0,
<vscale x 16 x i16> %1,
iXLen %2)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.mask.nxv16f16.iXLen(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x half> @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.mask.nxv16f16.iXLen(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vrgather.vv.nxv32f16.iXLen(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i16>,
iXLen)
define <vscale x 32 x half> @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.vv.nxv32f16.iXLen(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0,
<vscale x 32 x i16> %1,
iXLen %2)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vrgather.vv.mask.nxv32f16.iXLen(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.vv.mask.nxv32f16.iXLen(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.iXLen(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i32>,
iXLen)
define <vscale x 1 x float> @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.iXLen(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0,
<vscale x 1 x i32> %1,
iXLen %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vrgather.vv.mask.nxv1f32.iXLen(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x float> @intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.mask.nxv1f32.iXLen(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.iXLen(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i32>,
iXLen)
define <vscale x 2 x float> @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.iXLen(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0,
<vscale x 2 x i32> %1,
iXLen %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vrgather.vv.mask.nxv2f32.iXLen(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x float> @intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.mask.nxv2f32.iXLen(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.iXLen(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i32>,
iXLen)
define <vscale x 4 x float> @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.iXLen(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0,
<vscale x 4 x i32> %1,
iXLen %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vrgather.vv.mask.nxv4f32.iXLen(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x float> @intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.mask.nxv4f32.iXLen(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.iXLen(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i32>,
iXLen)
define <vscale x 8 x float> @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.iXLen(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0,
<vscale x 8 x i32> %1,
iXLen %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vrgather.vv.mask.nxv8f32.iXLen(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x float> @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.mask.nxv8f32.iXLen(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vrgather.vv.nxv16f32.iXLen(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i32>,
iXLen)
define <vscale x 16 x float> @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.nxv16f32.iXLen(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0,
<vscale x 16 x i32> %1,
iXLen %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vrgather.vv.mask.nxv16f32.iXLen(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.mask.nxv16f32.iXLen(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.iXLen(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i64>,
iXLen)
define <vscale x 1 x double> @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.iXLen(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0,
<vscale x 1 x i64> %1,
iXLen %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vrgather.vv.mask.nxv1f64.iXLen(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x double> @intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.mask.nxv1f64.iXLen(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.iXLen(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i64>,
iXLen)
define <vscale x 2 x double> @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.iXLen(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0,
<vscale x 2 x i64> %1,
iXLen %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vrgather.vv.mask.nxv2f64.iXLen(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x double> @intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.mask.nxv2f64.iXLen(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.iXLen(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i64>,
iXLen)
define <vscale x 4 x double> @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.iXLen(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0,
<vscale x 4 x i64> %1,
iXLen %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vrgather.vv.mask.nxv4f64.iXLen(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x double> @intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.mask.nxv4f64.iXLen(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vrgather.vv.nxv8f64.iXLen(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i64>,
iXLen)
define <vscale x 8 x double> @intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.nxv8f64.iXLen(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0,
<vscale x 8 x i64> %1,
iXLen %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vrgather.vv.mask.nxv8f64.iXLen(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x double> @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.mask.nxv8f64.iXLen(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x double> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.iXLen(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
iXLen,
iXLen)
define <vscale x 1 x i8> @intrinsic_vrgather_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.iXLen(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.iXLen(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i8> @intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.iXLen(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.iXLen(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
iXLen,
iXLen)
define <vscale x 2 x i8> @intrinsic_vrgather_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.iXLen(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.iXLen(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i8> @intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.iXLen(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.iXLen(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
iXLen,
iXLen)
define <vscale x 4 x i8> @intrinsic_vrgather_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.iXLen(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.iXLen(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i8> @intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.iXLen(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.iXLen(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen,
iXLen)
define <vscale x 8 x i8> @intrinsic_vrgather_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.iXLen(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.iXLen(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i8> @intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.iXLen(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.iXLen(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
iXLen,
iXLen)
define <vscale x 16 x i8> @intrinsic_vrgather_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.iXLen(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
iXLen %1,
iXLen %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.iXLen(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
iXLen,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x i8> @intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.iXLen(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.iXLen(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
iXLen,
iXLen)
define <vscale x 32 x i8> @intrinsic_vrgather_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.iXLen(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
iXLen %1,
iXLen %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.iXLen(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
iXLen,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x i8> @intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.iXLen(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.iXLen(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
iXLen,
iXLen)
define <vscale x 64 x i8> @intrinsic_vrgather_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.iXLen(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
iXLen %1,
iXLen %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.iXLen(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
iXLen,
<vscale x 64 x i1>,
iXLen,
iXLen)
define <vscale x 64 x i8> @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.iXLen(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
iXLen %2,
<vscale x 64 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.iXLen(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
iXLen,
iXLen)
define <vscale x 1 x i16> @intrinsic_vrgather_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.iXLen(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.iXLen(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i16> @intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.iXLen(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.iXLen(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
iXLen,
iXLen)
define <vscale x 2 x i16> @intrinsic_vrgather_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.iXLen(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.iXLen(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i16> @intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.iXLen(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.iXLen(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
iXLen,
iXLen)
define <vscale x 4 x i16> @intrinsic_vrgather_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.iXLen(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.iXLen(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i16> @intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.iXLen(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.iXLen(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
iXLen,
iXLen)
define <vscale x 8 x i16> @intrinsic_vrgather_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.iXLen(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.iXLen(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i16> @intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.iXLen(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.iXLen(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
iXLen,
iXLen)
define <vscale x 16 x i16> @intrinsic_vrgather_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.iXLen(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
iXLen %1,
iXLen %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.iXLen(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
iXLen,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x i16> @intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.iXLen(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.iXLen(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
iXLen,
iXLen)
define <vscale x 32 x i16> @intrinsic_vrgather_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.iXLen(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
iXLen %1,
iXLen %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.iXLen(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
iXLen,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x i16> @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.iXLen(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
iXLen %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.iXLen(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
iXLen,
iXLen)
define <vscale x 1 x i32> @intrinsic_vrgather_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.iXLen(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.iXLen(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i32> @intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.iXLen(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.iXLen(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
iXLen,
iXLen)
define <vscale x 2 x i32> @intrinsic_vrgather_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.iXLen(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.iXLen(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i32> @intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.iXLen(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
iXLen,
iXLen)
define <vscale x 4 x i32> @intrinsic_vrgather_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.iXLen(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i32> @intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.iXLen(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.iXLen(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
iXLen,
iXLen)
define <vscale x 8 x i32> @intrinsic_vrgather_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.iXLen(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.iXLen(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i32> @intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.iXLen(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.iXLen(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
iXLen,
iXLen)
define <vscale x 16 x i32> @intrinsic_vrgather_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.iXLen(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
iXLen %1,
iXLen %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.iXLen(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
iXLen,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x i32> @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.iXLen(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
iXLen %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.iXLen(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
iXLen,
iXLen)
define <vscale x 1 x i64> @intrinsic_vrgather_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.iXLen(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.iXLen(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x i64> @intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.iXLen(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.iXLen(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
iXLen,
iXLen)
define <vscale x 2 x i64> @intrinsic_vrgather_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.iXLen(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.iXLen(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x i64> @intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.iXLen(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.iXLen(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
iXLen,
iXLen)
define <vscale x 4 x i64> @intrinsic_vrgather_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.iXLen(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.iXLen(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x i64> @intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.iXLen(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.iXLen(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
iXLen,
iXLen)
define <vscale x 8 x i64> @intrinsic_vrgather_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.iXLen(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.iXLen(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x i64> @intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.iXLen(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.iXLen(
<vscale x 1 x half>,
<vscale x 1 x half>,
iXLen,
iXLen)
define <vscale x 1 x half> @intrinsic_vrgather_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.iXLen(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.mask.nxv1f16.iXLen(
<vscale x 1 x half>,
<vscale x 1 x half>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x half> @intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.mask.nxv1f16.iXLen(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.iXLen(
<vscale x 2 x half>,
<vscale x 2 x half>,
iXLen,
iXLen)
define <vscale x 2 x half> @intrinsic_vrgather_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.iXLen(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.mask.nxv2f16.iXLen(
<vscale x 2 x half>,
<vscale x 2 x half>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x half> @intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.mask.nxv2f16.iXLen(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.iXLen(
<vscale x 4 x half>,
<vscale x 4 x half>,
iXLen,
iXLen)
define <vscale x 4 x half> @intrinsic_vrgather_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.iXLen(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.mask.nxv4f16.iXLen(
<vscale x 4 x half>,
<vscale x 4 x half>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x half> @intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.mask.nxv4f16.iXLen(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.iXLen(
<vscale x 8 x half>,
<vscale x 8 x half>,
iXLen,
iXLen)
define <vscale x 8 x half> @intrinsic_vrgather_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.iXLen(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.mask.nxv8f16.iXLen(
<vscale x 8 x half>,
<vscale x 8 x half>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x half> @intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.mask.nxv8f16.iXLen(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.iXLen(
<vscale x 16 x half>,
<vscale x 16 x half>,
iXLen,
iXLen)
define <vscale x 16 x half> @intrinsic_vrgather_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.iXLen(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0,
iXLen %1,
iXLen %2)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vrgather.vx.mask.nxv16f16.iXLen(
<vscale x 16 x half>,
<vscale x 16 x half>,
iXLen,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x half> @intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.mask.nxv16f16.iXLen(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
iXLen %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vrgather.vx.nxv32f16.iXLen(
<vscale x 32 x half>,
<vscale x 32 x half>,
iXLen,
iXLen)
define <vscale x 32 x half> @intrinsic_vrgather_vx_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.nxv32f16.iXLen(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0,
iXLen %1,
iXLen %2)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vrgather.vx.mask.nxv32f16.iXLen(
<vscale x 32 x half>,
<vscale x 32 x half>,
iXLen,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x half> @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.mask.nxv32f16.iXLen(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
iXLen %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.iXLen(
<vscale x 1 x float>,
<vscale x 1 x float>,
iXLen,
iXLen)
define <vscale x 1 x float> @intrinsic_vrgather_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.iXLen(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.iXLen(
<vscale x 1 x float>,
<vscale x 1 x float>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x float> @intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.iXLen(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.iXLen(
<vscale x 2 x float>,
<vscale x 2 x float>,
iXLen,
iXLen)
define <vscale x 2 x float> @intrinsic_vrgather_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.iXLen(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.iXLen(
<vscale x 2 x float>,
<vscale x 2 x float>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x float> @intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.iXLen(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.iXLen(
<vscale x 4 x float>,
<vscale x 4 x float>,
iXLen,
iXLen)
define <vscale x 4 x float> @intrinsic_vrgather_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.iXLen(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.iXLen(
<vscale x 4 x float>,
<vscale x 4 x float>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x float> @intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.iXLen(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.iXLen(
<vscale x 8 x float>,
<vscale x 8 x float>,
iXLen,
iXLen)
define <vscale x 8 x float> @intrinsic_vrgather_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.iXLen(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.iXLen(
<vscale x 8 x float>,
<vscale x 8 x float>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x float> @intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.iXLen(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.iXLen(
<vscale x 16 x float>,
<vscale x 16 x float>,
iXLen,
iXLen)
define <vscale x 16 x float> @intrinsic_vrgather_vx_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.iXLen(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0,
iXLen %1,
iXLen %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.iXLen(
<vscale x 16 x float>,
<vscale x 16 x float>,
iXLen,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x float> @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.iXLen(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
iXLen %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.iXLen(
<vscale x 1 x double>,
<vscale x 1 x double>,
iXLen,
iXLen)
define <vscale x 1 x double> @intrinsic_vrgather_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.iXLen(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.iXLen(
<vscale x 1 x double>,
<vscale x 1 x double>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x double> @intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.iXLen(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.iXLen(
<vscale x 2 x double>,
<vscale x 2 x double>,
iXLen,
iXLen)
define <vscale x 2 x double> @intrinsic_vrgather_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.iXLen(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.iXLen(
<vscale x 2 x double>,
<vscale x 2 x double>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x double> @intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.iXLen(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.iXLen(
<vscale x 4 x double>,
<vscale x 4 x double>,
iXLen,
iXLen)
define <vscale x 4 x double> @intrinsic_vrgather_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.iXLen(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.iXLen(
<vscale x 4 x double>,
<vscale x 4 x double>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x double> @intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.iXLen(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.iXLen(
<vscale x 8 x double>,
<vscale x 8 x double>,
iXLen,
iXLen)
define <vscale x 8 x double> @intrinsic_vrgather_vx_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.iXLen(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.iXLen(
<vscale x 8 x double>,
<vscale x 8 x double>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x double> @intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.iXLen(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x double> %a
}
define <vscale x 1 x i8> @intrinsic_vrgather_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.iXLen(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x i8> %a
}
define <vscale x 1 x i8> @intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.iXLen(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vrgather_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.iXLen(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.iXLen(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vrgather_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.iXLen(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.iXLen(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vrgather_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.iXLen(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.iXLen(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vrgather_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.iXLen(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
iXLen 9,
iXLen %1)
ret <vscale x 16 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.iXLen(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen 9,
<vscale x 16 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vrgather_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.iXLen(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
iXLen 9,
iXLen %1)
ret <vscale x 32 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.iXLen(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen 9,
<vscale x 32 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vrgather_vi_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.iXLen(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
iXLen 9,
iXLen %1)
ret <vscale x 64 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.iXLen(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
iXLen 9,
<vscale x 64 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 64 x i8> %a
}
define <vscale x 1 x i16> @intrinsic_vrgather_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.iXLen(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x i16> %a
}
define <vscale x 1 x i16> @intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.iXLen(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vrgather_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.iXLen(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.iXLen(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vrgather_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.iXLen(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.iXLen(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vrgather_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.iXLen(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.iXLen(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vrgather_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.iXLen(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
iXLen 9,
iXLen %1)
ret <vscale x 16 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.iXLen(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen 9,
<vscale x 16 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vrgather_vi_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.iXLen(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
iXLen 9,
iXLen %1)
ret <vscale x 32 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.iXLen(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
iXLen 9,
<vscale x 32 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a
}
define <vscale x 1 x i32> @intrinsic_vrgather_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.iXLen(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x i32> %a
}
define <vscale x 1 x i32> @intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.iXLen(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vrgather_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.iXLen(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.iXLen(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vrgather_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.iXLen(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vrgather_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.iXLen(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.iXLen(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vrgather_vi_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.iXLen(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
iXLen 9,
iXLen %1)
ret <vscale x 16 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.iXLen(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
iXLen 9,
<vscale x 16 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a
}
define <vscale x 1 x i64> @intrinsic_vrgather_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.iXLen(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.iXLen(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vrgather_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.iXLen(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.iXLen(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vrgather_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.iXLen(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.iXLen(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vrgather_vi_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.iXLen(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.iXLen(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x i64> %a
}
define <vscale x 1 x half> @intrinsic_vrgather_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.iXLen(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x half> %a
}
define <vscale x 1 x half> @intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.mask.nxv1f16.iXLen(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a
}
define <vscale x 2 x half> @intrinsic_vrgather_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.iXLen(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x half> %a
}
define <vscale x 2 x half> @intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.mask.nxv2f16.iXLen(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a
}
define <vscale x 4 x half> @intrinsic_vrgather_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.iXLen(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x half> %a
}
define <vscale x 4 x half> @intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.mask.nxv4f16.iXLen(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a
}
define <vscale x 8 x half> @intrinsic_vrgather_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.iXLen(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x half> %a
}
define <vscale x 8 x half> @intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.mask.nxv8f16.iXLen(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a
}
define <vscale x 16 x half> @intrinsic_vrgather_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.iXLen(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0,
iXLen 9,
iXLen %1)
ret <vscale x 16 x half> %a
}
define <vscale x 16 x half> @intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.mask.nxv16f16.iXLen(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
iXLen 9,
<vscale x 16 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a
}
define <vscale x 32 x half> @intrinsic_vrgather_vi_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.nxv32f16.iXLen(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0,
iXLen 9,
iXLen %1)
ret <vscale x 32 x half> %a
}
define <vscale x 32 x half> @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.mask.nxv32f16.iXLen(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
iXLen 9,
<vscale x 32 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a
}
define <vscale x 1 x float> @intrinsic_vrgather_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.iXLen(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x float> %a
}
define <vscale x 1 x float> @intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.iXLen(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a
}
define <vscale x 2 x float> @intrinsic_vrgather_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.iXLen(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x float> %a
}
define <vscale x 2 x float> @intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.iXLen(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a
}
define <vscale x 4 x float> @intrinsic_vrgather_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.iXLen(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x float> %a
}
define <vscale x 4 x float> @intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.iXLen(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a
}
define <vscale x 8 x float> @intrinsic_vrgather_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.iXLen(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x float> %a
}
define <vscale x 8 x float> @intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.iXLen(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a
}
define <vscale x 16 x float> @intrinsic_vrgather_vi_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.iXLen(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0,
iXLen 9,
iXLen %1)
ret <vscale x 16 x float> %a
}
define <vscale x 16 x float> @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.iXLen(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
iXLen 9,
<vscale x 16 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a
}
define <vscale x 1 x double> @intrinsic_vrgather_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.iXLen(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x double> %a
}
define <vscale x 1 x double> @intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.iXLen(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a
}
define <vscale x 2 x double> @intrinsic_vrgather_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.iXLen(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x double> %a
}
define <vscale x 2 x double> @intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.iXLen(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a
}
define <vscale x 4 x double> @intrinsic_vrgather_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.iXLen(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x double> %a
}
define <vscale x 4 x double> @intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.iXLen(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a
}
define <vscale x 8 x double> @intrinsic_vrgather_vi_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.iXLen(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x double> %a
}
define <vscale x 8 x double> @intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.iXLen(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x double> %a
}
declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.iXLen(
<vscale x 1 x bfloat>,
<vscale x 1 x bfloat>,
<vscale x 1 x i16>,
iXLen)
define <vscale x 1 x bfloat> @intrinsic_vrgather_vv_nxv1bf16_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1bf16_nxv1bf16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.iXLen(
<vscale x 1 x bfloat> undef,
<vscale x 1 x bfloat> %0,
<vscale x 1 x i16> %1,
iXLen %2)
ret <vscale x 1 x bfloat> %a
}
declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv1bf16.iXLen(
<vscale x 1 x bfloat>,
<vscale x 1 x bfloat>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x bfloat> @intrinsic_vrgather_mask_vv_nxv1bf16_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1bf16_nxv1bf16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv1bf16.iXLen(
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x bfloat> %a
}
declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.iXLen(
<vscale x 2 x bfloat>,
<vscale x 2 x bfloat>,
<vscale x 2 x i16>,
iXLen)
define <vscale x 2 x bfloat> @intrinsic_vrgather_vv_nxv2bf16_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2bf16_nxv2bf16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.iXLen(
<vscale x 2 x bfloat> undef,
<vscale x 2 x bfloat> %0,
<vscale x 2 x i16> %1,
iXLen %2)
ret <vscale x 2 x bfloat> %a
}
declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv2bf16.iXLen(
<vscale x 2 x bfloat>,
<vscale x 2 x bfloat>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x bfloat> @intrinsic_vrgather_mask_vv_nxv2bf16_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2bf16_nxv2bf16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv2bf16.iXLen(
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x bfloat> %a
}
declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.iXLen(
<vscale x 4 x bfloat>,
<vscale x 4 x bfloat>,
<vscale x 4 x i16>,
iXLen)
define <vscale x 4 x bfloat> @intrinsic_vrgather_vv_nxv4bf16_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4bf16_nxv4bf16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.iXLen(
<vscale x 4 x bfloat> undef,
<vscale x 4 x bfloat> %0,
<vscale x 4 x i16> %1,
iXLen %2)
ret <vscale x 4 x bfloat> %a
}
declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv4bf16.iXLen(
<vscale x 4 x bfloat>,
<vscale x 4 x bfloat>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x bfloat> @intrinsic_vrgather_mask_vv_nxv4bf16_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4bf16_nxv4bf16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv4bf16.iXLen(
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x bfloat> %a
}
declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.iXLen(
<vscale x 8 x bfloat>,
<vscale x 8 x bfloat>,
<vscale x 8 x i16>,
iXLen)
define <vscale x 8 x bfloat> @intrinsic_vrgather_vv_nxv8bf16_nxv8bf16_nxv8i16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8bf16_nxv8bf16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.iXLen(
<vscale x 8 x bfloat> undef,
<vscale x 8 x bfloat> %0,
<vscale x 8 x i16> %1,
iXLen %2)
ret <vscale x 8 x bfloat> %a
}
declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv8bf16.iXLen(
<vscale x 8 x bfloat>,
<vscale x 8 x bfloat>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x bfloat> @intrinsic_vrgather_mask_vv_nxv8bf16_nxv8bf16_nxv8i16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8bf16_nxv8bf16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv8bf16.iXLen(
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x bfloat> %a
}
declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.iXLen(
<vscale x 16 x bfloat>,
<vscale x 16 x bfloat>,
<vscale x 16 x i16>,
iXLen)
define <vscale x 16 x bfloat> @intrinsic_vrgather_vv_nxv16bf16_nxv16bf16_nxv16i16(<vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16bf16_nxv16bf16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.iXLen(
<vscale x 16 x bfloat> undef,
<vscale x 16 x bfloat> %0,
<vscale x 16 x i16> %1,
iXLen %2)
ret <vscale x 16 x bfloat> %a
}
declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv16bf16.iXLen(
<vscale x 16 x bfloat>,
<vscale x 16 x bfloat>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x bfloat> @intrinsic_vrgather_mask_vv_nxv16bf16_nxv16bf16_nxv16i16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16bf16_nxv16bf16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv16bf16.iXLen(
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x bfloat> %a
}
declare <vscale x 32 x bfloat> @llvm.riscv.vrgather.vv.nxv32bf16.iXLen(
<vscale x 32 x bfloat>,
<vscale x 32 x bfloat>,
<vscale x 32 x i16>,
iXLen)
define <vscale x 32 x bfloat> @intrinsic_vrgather_vv_nxv32bf16_nxv32bf16_nxv32i16(<vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vv_nxv32bf16_nxv32bf16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmv.v.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vv.nxv32bf16.iXLen(
<vscale x 32 x bfloat> undef,
<vscale x 32 x bfloat> %0,
<vscale x 32 x i16> %1,
iXLen %2)
ret <vscale x 32 x bfloat> %a
}
declare <vscale x 32 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv32bf16.iXLen(
<vscale x 32 x bfloat>,
<vscale x 32 x bfloat>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x bfloat> @intrinsic_vrgather_mask_vv_nxv32bf16_nxv32bf16_nxv32i16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32bf16_nxv32bf16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv32bf16.iXLen(
<vscale x 32 x bfloat> %0,
<vscale x 32 x bfloat> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x bfloat> %a
}
declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.iXLen(
<vscale x 1 x bfloat>,
<vscale x 1 x bfloat>,
iXLen,
iXLen)
define <vscale x 1 x bfloat> @intrinsic_vrgather_vx_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.iXLen(
<vscale x 1 x bfloat> undef,
<vscale x 1 x bfloat> %0,
iXLen %1,
iXLen %2)
ret <vscale x 1 x bfloat> %a
}
declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv1bf16.iXLen(
<vscale x 1 x bfloat>,
<vscale x 1 x bfloat>,
iXLen,
<vscale x 1 x i1>,
iXLen,
iXLen)
define <vscale x 1 x bfloat> @intrinsic_vrgather_mask_vx_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv1bf16.iXLen(
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
iXLen %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x bfloat> %a
}
declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.iXLen(
<vscale x 2 x bfloat>,
<vscale x 2 x bfloat>,
iXLen,
iXLen)
define <vscale x 2 x bfloat> @intrinsic_vrgather_vx_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.iXLen(
<vscale x 2 x bfloat> undef,
<vscale x 2 x bfloat> %0,
iXLen %1,
iXLen %2)
ret <vscale x 2 x bfloat> %a
}
declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv2bf16.iXLen(
<vscale x 2 x bfloat>,
<vscale x 2 x bfloat>,
iXLen,
<vscale x 2 x i1>,
iXLen,
iXLen)
define <vscale x 2 x bfloat> @intrinsic_vrgather_mask_vx_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv2bf1bf16XLen(
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
iXLen %2,
<vscale x 2 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 2 x bfloat> %a
}
declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.iXLen(
<vscale x 4 x bfloat>,
<vscale x 4 x bfloat>,
iXLen,
iXLen)
define <vscale x 4 x bfloat> @intrinsic_vrgather_vx_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vx v9, v8, a0
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.iXLen(
<vscale x 4 x bfloat> undef,
<vscale x 4 x bfloat> %0,
iXLen %1,
iXLen %2)
ret <vscale x 4 x bfloat> %a
}
declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv4bf16.iXLen(
<vscale x 4 x bfloat>,
<vscale x 4 x bfloat>,
iXLen,
<vscale x 4 x i1>,
iXLen,
iXLen)
define <vscale x 4 x bfloat> @intrinsic_vrgather_mask_vx_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv4bf16.iXLen(
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
iXLen %2,
<vscale x 4 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 4 x bfloat> %a
}
declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.iXLen(
<vscale x 8 x bfloat>,
<vscale x 8 x bfloat>,
iXLen,
iXLen)
define <vscale x 8 x bfloat> @intrinsic_vrgather_vx_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vx v10, v8, a0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.iXLen(
<vscale x 8 x bfloat> undef,
<vscale x 8 x bfloat> %0,
iXLen %1,
iXLen %2)
ret <vscale x 8 x bfloat> %a
}
declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv8bf16.iXLen(
<vscale x 8 x bfloat>,
<vscale x 8 x bfloat>,
iXLen,
<vscale x 8 x i1>,
iXLen,
iXLen)
define <vscale x 8 x bfloat> @intrinsic_vrgather_mask_vx_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv8bf16.iXLen(
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
iXLen %2,
<vscale x 8 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 8 x bfloat> %a
}
declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.nxv16bf16.iXLen(
<vscale x 16 x bfloat>,
<vscale x 16 x bfloat>,
iXLen,
iXLen)
define <vscale x 16 x bfloat> @intrinsic_vrgather_vx_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vx v12, v8, a0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.nxv16bf16.iXLen(
<vscale x 16 x bfloat> undef,
<vscale x 16 x bfloat> %0,
iXLen %1,
iXLen %2)
ret <vscale x 16 x bfloat> %a
}
declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv16bf16.iXLen(
<vscale x 16 x bfloat>,
<vscale x 16 x bfloat>,
iXLen,
<vscale x 16 x i1>,
iXLen,
iXLen)
define <vscale x 16 x bfloat> @intrinsic_vrgather_mask_vx_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv16bf16.iXLen(
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
iXLen %2,
<vscale x 16 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 16 x bfloat> %a
}
declare <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.nxv32bf16.iXLen(
<vscale x 32 x bfloat>,
<vscale x 32 x bfloat>,
iXLen,
iXLen)
define <vscale x 32 x bfloat> @intrinsic_vrgather_vx_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vx_nxv32bf16_nxv32bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vx v16, v8, a0
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.nxv32bf16.iXLen(
<vscale x 32 x bfloat> undef,
<vscale x 32 x bfloat> %0,
iXLen %1,
iXLen %2)
ret <vscale x 32 x bfloat> %a
}
declare <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv32bf16.iXLen(
<vscale x 32 x bfloat>,
<vscale x 32 x bfloat>,
iXLen,
<vscale x 32 x i1>,
iXLen,
iXLen)
define <vscale x 32 x bfloat> @intrinsic_vrgather_mask_vx_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32bf16_nxv32bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv32bf16.iXLen(
<vscale x 32 x bfloat> %0,
<vscale x 32 x bfloat> %1,
iXLen %2,
<vscale x 32 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 32 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vrgather_vi_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.iXLen(
<vscale x 1 x bfloat> undef,
<vscale x 1 x bfloat> %0,
iXLen 9,
iXLen %1)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vrgather_mask_vi_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv1bf16.iXLen(
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
iXLen 9,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vrgather_vi_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.iXLen(
<vscale x 2 x bfloat> undef,
<vscale x 2 x bfloat> %0,
iXLen 9,
iXLen %1)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vrgather_mask_vi_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv2bf16.iXLen(
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
iXLen 9,
<vscale x 2 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vrgather_vi_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 9
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.iXLen(
<vscale x 4 x bfloat> undef,
<vscale x 4 x bfloat> %0,
iXLen 9,
iXLen %1)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vrgather_mask_vi_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv4bf16.iXLen(
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
iXLen 9,
<vscale x 4 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vrgather_vi_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 9
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.iXLen(
<vscale x 8 x bfloat> undef,
<vscale x 8 x bfloat> %0,
iXLen 9,
iXLen %1)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vrgather_mask_vi_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv8bf16.iXLen(
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
iXLen 9,
<vscale x 8 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vrgather_vi_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrgather.vi v12, v8, 9
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.nxv16bf16.iXLen(
<vscale x 16 x bfloat> undef,
<vscale x 16 x bfloat> %0,
iXLen 9,
iXLen %1)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vrgather_mask_vi_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv16bf16.iXLen(
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
iXLen 9,
<vscale x 16 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 32 x bfloat> @intrinsic_vrgather_vi_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrgather_vi_nxv32bf16_nxv32bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrgather.vi v16, v8, 9
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.nxv32bf16.iXLen(
<vscale x 32 x bfloat> undef,
<vscale x 32 x bfloat> %0,
iXLen 9,
iXLen %1)
ret <vscale x 32 x bfloat> %a
}
define <vscale x 32 x bfloat> @intrinsic_vrgather_mask_vi_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32bf16_nxv32bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv32bf16.iXLen(
<vscale x 32 x bfloat> %0,
<vscale x 32 x bfloat> %1,
iXLen 9,
<vscale x 32 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 32 x bfloat> %a
}
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