EmulateInstructionMIPS.cpp | Explore in Territory

//===-- EmulateInstructionMIPS.cpp ----------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "EmulateInstructionMIPS.h"

#include <cstdlib>
#include <optional>

#include "lldb/Core/Address.h"
#include "lldb/Core/Opcode.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Symbol/UnwindPlan.h"
#include "lldb/Target/Target.h"
#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/ConstString.h"
#include "lldb/Utility/DataExtractor.h"
#include "lldb/Utility/RegisterValue.h"
#include "lldb/Utility/Stream.h"
#include "llvm-c/Disassembler.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"

#include "llvm/ADT/STLExtras.h"

#include "Plugins/Process/Utility/InstructionUtils.h"
#include "Plugins/Process/Utility/RegisterContext_mips.h"

usingnamespacelldb;
usingnamespacelldb_private;

LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionMIPS, InstructionMIPS)

#define UInt(x) …
#define integer …

//
// EmulateInstructionMIPS implementation
//

#ifdef __mips__
extern "C" {
void LLVMInitializeMipsTargetInfo();
void LLVMInitializeMipsTarget();
void LLVMInitializeMipsAsmPrinter();
void LLVMInitializeMipsTargetMC();
void LLVMInitializeMipsDisassembler();
}
#endif

EmulateInstructionMIPS::EmulateInstructionMIPS(
    const lldb_private::ArchSpec &arch)
    : … { … }

void EmulateInstructionMIPS::Initialize() { … }

void EmulateInstructionMIPS::Terminate() { … }

llvm::StringRef EmulateInstructionMIPS::GetPluginDescriptionStatic() { … }

EmulateInstruction *
EmulateInstructionMIPS::CreateInstance(const ArchSpec &arch,
                                       InstructionType inst_type) { … }

bool EmulateInstructionMIPS::SetTargetTriple(const ArchSpec &arch) { … }

const char *EmulateInstructionMIPS::GetRegisterName(unsigned reg_num,
                                                    bool alternate_name) { … }

std::optional<RegisterInfo>
EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,
                                        uint32_t reg_num) { … }

EmulateInstructionMIPS::MipsOpcode *
EmulateInstructionMIPS::GetOpcodeForInstruction(llvm::StringRef name) { … }

uint32_t
EmulateInstructionMIPS::GetSizeOfInstruction(lldb_private::DataExtractor &data,
                                             uint64_t inst_addr) { … }

bool EmulateInstructionMIPS::SetInstruction(const Opcode &insn_opcode,
                                            const Address &inst_addr,
                                            Target *target) { … }

bool EmulateInstructionMIPS::ReadInstruction() { … }

bool EmulateInstructionMIPS::EvaluateInstruction(uint32_t evaluate_options) { … }

bool EmulateInstructionMIPS::CreateFunctionEntryUnwind(
    UnwindPlan &unwind_plan) { … }

bool EmulateInstructionMIPS::nonvolatile_reg_p(uint32_t regnum) { … }

bool EmulateInstructionMIPS::Emulate_ADDiu(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_SW(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_LW(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_SUBU_ADDU(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_LUI(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_ADDIUSP(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_ADDIUS5(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_SWSP(llvm::MCInst &insn) { … }

/* Emulate SWM16,SWM32 and SWP instruction.

   SWM16 always has stack pointer as a base register (but it is still available
   in MCInst as an operand).
   SWM32 and SWP can have base register other than stack pointer.
*/
bool EmulateInstructionMIPS::Emulate_SWM16_32(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_LWSP(llvm::MCInst &insn) { … }

/* Emulate LWM16, LWM32 and LWP instructions.

   LWM16 always has stack pointer as a base register (but it is still available
   in MCInst as an operand).
   LWM32 and LWP can have base register other than stack pointer.
*/
bool EmulateInstructionMIPS::Emulate_LWM16_32(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_JRADDIUSP(llvm::MCInst &insn) { … }

static int IsAdd64bitOverflow(int32_t a, int32_t b) { … }

/*
    Emulate below MIPS branch instructions.
    BEQ, BNE : Branch on condition
    BEQL, BNEL : Branch likely
*/
bool EmulateInstructionMIPS::Emulate_BXX_3ops(llvm::MCInst &insn) { … }

/*
    Emulate below MIPS branch instructions.
    BEQC, BNEC, BLTC, BGEC, BLTUC, BGEUC, BOVC, BNVC: Compact branch
   instructions with no delay slot
*/
bool EmulateInstructionMIPS::Emulate_BXX_3ops_C(llvm::MCInst &insn) { … }

/*
    Emulate below MIPS conditional branch and link instructions.
    BLEZALC, BGEZALC, BLTZALC, BGTZALC, BEQZALC, BNEZALC : Compact branches
*/
bool EmulateInstructionMIPS::Emulate_Bcond_Link_C(llvm::MCInst &insn) { … }

/*
    Emulate below MIPS Non-Compact conditional branch and link instructions.
    BLTZAL, BGEZAL      :
    BLTZALL, BGEZALL    : Branch likely
*/
bool EmulateInstructionMIPS::Emulate_Bcond_Link(llvm::MCInst &insn) { … }

/*
    Emulate below MIPS branch instructions.
    BLTZL, BGEZL, BGTZL, BLEZL : Branch likely
    BLTZ, BGEZ, BGTZ, BLEZ     : Non-compact branches
*/
bool EmulateInstructionMIPS::Emulate_BXX_2ops(llvm::MCInst &insn) { … }

/*
    Emulate below MIPS branch instructions.
    BLTZC, BLEZC, BGEZC, BGTZC, BEQZC, BNEZC : Compact Branches
*/
bool EmulateInstructionMIPS::Emulate_BXX_2ops_C(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_B16_MM(llvm::MCInst &insn) { … }

/*
   BEQZC, BNEZC are 32 bit compact instructions without a delay slot.
   BEQZ16, BNEZ16 are 16 bit instructions with delay slot.
   BGEZALS, BLTZALS are 16 bit instructions with short (2-byte) delay slot.
*/
bool EmulateInstructionMIPS::Emulate_Branch_MM(llvm::MCInst &insn) { … }

/* Emulate micromips jump instructions.
   JALR16,JALRS16
*/
bool EmulateInstructionMIPS::Emulate_JALRx16_MM(llvm::MCInst &insn) { … }

/* Emulate JALS and JALX instructions.
    JALS 32 bit instruction with short (2-byte) delay slot.
    JALX 32 bit instruction with 4-byte delay slot.
*/
bool EmulateInstructionMIPS::Emulate_JALx(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_JALRS(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BAL(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BALC(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BC(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_J(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_JAL(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_JALR(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_JIALC(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_JIC(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_JR(llvm::MCInst &insn) { … }

/*
    Emulate Branch on FP True/False
    BC1F, BC1FL :   Branch on FP False (L stands for branch likely)
    BC1T, BC1TL :   Branch on FP True  (L stands for branch likely)
*/
bool EmulateInstructionMIPS::Emulate_FP_branch(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BC1EQZ(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BC1NEZ(llvm::MCInst &insn) { … }

/*
    Emulate MIPS-3D Branch instructions
    BC1ANY2F, BC1ANY2T  : Branch on Any of Two Floating Point Condition Codes
   False/True
    BC1ANY4F, BC1ANY4T  : Branch on Any of Four Floating Point Condition Codes
   False/True
*/
bool EmulateInstructionMIPS::Emulate_3D_branch(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BNZB(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BNZH(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BNZW(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BNZD(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BZB(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BZH(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BZW(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BZD(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_MSA_Branch_DF(llvm::MCInst &insn,
                                                   int element_byte_size,
                                                   bool bnz) { … }

bool EmulateInstructionMIPS::Emulate_BNZV(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_BZV(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_MSA_Branch_V(llvm::MCInst &insn,
                                                  bool bnz) { … }

bool EmulateInstructionMIPS::Emulate_LDST_Imm(llvm::MCInst &insn) { … }

bool EmulateInstructionMIPS::Emulate_LDST_Reg(llvm::MCInst &insn) { … }
llvm/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
