llvm/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

//===-- TestRISCVEmulator.cpp ---------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "gtest/gtest.h"

#include "lldb/Core/Address.h"
#include "lldb/Core/Disassembler.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Target/ExecutionContext.h"
#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/RegisterValue.h"

#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"

usingnamespacellvm;
usingnamespacelldb;
usingnamespacelldb_private;

struct RISCVEmulatorTester : public EmulateInstructionRISCV, testing::Test { … };

TEST_F(RISCVEmulatorTester, testJAL) { … }

constexpr uint32_t EncodeIType(uint32_t opcode, uint32_t funct3, uint32_t rd,
                               uint32_t rs1, uint32_t imm) { … }

constexpr uint32_t EncodeJALR(uint32_t rd, uint32_t rs1, int32_t offset) { … }

TEST_F(RISCVEmulatorTester, testJALR) { … }

constexpr uint32_t EncodeBType(uint32_t opcode, uint32_t funct3, uint32_t rs1,
                               uint32_t rs2, uint32_t imm) { … }

constexpr uint32_t BEQ(uint32_t rs1, uint32_t rs2, int32_t offset) { … }

constexpr uint32_t BNE(uint32_t rs1, uint32_t rs2, int32_t offset) { … }

constexpr uint32_t BLT(uint32_t rs1, uint32_t rs2, int32_t offset) { … }

constexpr uint32_t BGE(uint32_t rs1, uint32_t rs2, int32_t offset) { … }

constexpr uint32_t BLTU(uint32_t rs1, uint32_t rs2, int32_t offset) { … }

constexpr uint32_t BGEU(uint32_t rs1, uint32_t rs2, int32_t offset) { … }

EncoderB;

static void testBranch(RISCVEmulatorTester *tester, EncoderB encoder,
                       bool branched, uint64_t rs1, uint64_t rs2) { … }

#define GEN_BRANCH_TEST(name, rs1, rs2_branched, rs2_continued) …

static void CheckRD(RISCVEmulatorTester *tester, uint64_t rd, uint64_t value) { … }

template <typename T>
static void CheckMem(RISCVEmulatorTester *tester, uint64_t addr,
                     uint64_t value) { … }

RS1;
RS2;
PC;
RDComputer;

static void TestInst(RISCVEmulatorTester *tester, DecodeResult inst,
                     bool has_rs2, RDComputer rd_val) { … }

template <typename T>
static void TestAtomic(RISCVEmulatorTester *tester, uint64_t inst, T rs1_val,
                       T rs2_val, T rd_expected, T mem_expected) { … }

TEST_F(RISCVEmulatorTester, TestAtomicSequence) { … }

struct TestDecode { … };

TEST_F(RISCVEmulatorTester, TestCDecode) { … }

class RISCVEmulatorTester32 : public RISCVEmulatorTester { … };

TEST_F(RISCVEmulatorTester32, TestCDecodeRV32) { … }

// GEN_BRANCH_TEST(opcode, imm1, imm2, imm3):
// It should branch for instruction `opcode imm1, imm2`
// It should do nothing for instruction `opcode imm1, imm3`
GEN_BRANCH_TEST(…)
GEN_BRANCH_TEST(…)
GEN_BRANCH_TEST(…)
GEN_BRANCH_TEST(…)
GEN_BRANCH_TEST(…)
GEN_BRANCH_TEST(…)

struct TestData { … };

TEST_F(RISCVEmulatorTester, TestDecodeAndExcute) { … }

TEST_F(RISCVEmulatorTester, TestAMOSWAP) { … }

TEST_F(RISCVEmulatorTester, TestAMOADD) { … }

TEST_F(RISCVEmulatorTester, TestAMOXOR) { … }

TEST_F(RISCVEmulatorTester, TestAMOAND) { … }

TEST_F(RISCVEmulatorTester, TestAMOOR) { … }

TEST_F(RISCVEmulatorTester, TestAMOMIN) { … }

TEST_F(RISCVEmulatorTester, TestAMOMAX) { … }

TEST_F(RISCVEmulatorTester, TestAMOMINU) { … }

TEST_F(RISCVEmulatorTester, TestAMOMAXU) { … }

template <typename T> struct F_D_CalInst { … };

FloatCalInst;
DoubleCalInst;

template <typename T>
static void TestF_D_CalInst(RISCVEmulatorTester *tester, DecodeResult inst,
                            T rs1_val, T rs2_val, T rd_exp) { … }

TEST_F(RISCVEmulatorTester, TestFloatInst) { … }

TEST_F(RISCVEmulatorTester, TestDoubleInst) { … }

template <typename T>
static void TestInverse(RISCVEmulatorTester *tester, uint32_t f_reg,
                        uint32_t x_reg, DecodeResult f2i, DecodeResult i2f,
                        APFloat apf_val) { … }

struct FCVTInst { … };

TEST_F(RISCVEmulatorTester, TestFCVT) { … }

TEST_F(RISCVEmulatorTester, TestFDInverse) { … }

TEST_F(RISCVEmulatorTester, TestFloatLSInst) { … }

TEST_F(RISCVEmulatorTester, TestDoubleLSInst) { … }

TEST_F(RISCVEmulatorTester, TestFMV_X_WInst) { … }

TEST_F(RISCVEmulatorTester, TestFMV_X_DInst) { … }

TEST_F(RISCVEmulatorTester, TestFMV_W_XInst) { … }

TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) { … }