llvm/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp

//===-- MCInstrDescView.cpp -------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "MCInstrDescView.h"

#include <iterator>
#include <tuple>

#include "llvm/ADT/STLExtras.h"

namespace llvm {
namespace exegesis {

unsigned Variable::getIndex() const { … }

unsigned Variable::getPrimaryOperandIndex() const { … }

bool Variable::hasTiedOperands() const { … }

unsigned Operand::getIndex() const { … }

bool Operand::isExplicit() const { … }

bool Operand::isImplicit() const { … }

bool Operand::isImplicitReg() const { … }

bool Operand::isDef() const { … }

bool Operand::isUse() const { … }

bool Operand::isReg() const { … }

bool Operand::isTied() const { … }

bool Operand::isVariable() const { … }

bool Operand::isMemory() const { … }

bool Operand::isImmediate() const { … }

unsigned Operand::getTiedToIndex() const { … }

unsigned Operand::getVariableIndex() const { … }

unsigned Operand::getImplicitReg() const { … }

const RegisterAliasingTracker &Operand::getRegisterAliasing() const { … }

const MCOperandInfo &Operand::getExplicitOperandInfo() const { … }

const BitVector *BitVectorCache::getUnique(BitVector &&BV) const { … }

Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
                         SmallVector<Operand, 8> Operands,
                         SmallVector<Variable, 4> Variables,
                         const BitVector *ImplDefRegs,
                         const BitVector *ImplUseRegs,
                         const BitVector *AllDefRegs,
                         const BitVector *AllUseRegs)
    : … { … }

std::unique_ptr<Instruction>
Instruction::create(const MCInstrInfo &InstrInfo,
                    const RegisterAliasingTrackerCache &RATC,
                    const BitVectorCache &BVC, unsigned Opcode) { … }

const Operand &Instruction::getPrimaryOperand(const Variable &Var) const { … }

bool Instruction::hasMemoryOperands() const { … }

bool Instruction::hasAliasingImplicitRegisters() const { … }

// Returns true if there are registers that are both in `A` and `B` but not in
// `Forbidden`.
static bool anyCommonExcludingForbidden(const BitVector &A, const BitVector &B,
                                        const BitVector &Forbidden) { … }

bool Instruction::hasAliasingRegistersThrough(
    const Instruction &OtherInstr, const BitVector &ForbiddenRegisters) const { … }

bool Instruction::hasTiedRegisters() const { … }

bool Instruction::hasAliasingRegisters(
    const BitVector &ForbiddenRegisters) const { … }

bool Instruction::hasOneUseOrOneDef() const { … }

void Instruction::dump(const MCRegisterInfo &RegInfo,
                       const RegisterAliasingTrackerCache &RATC,
                       raw_ostream &Stream) const { … }

InstructionsCache::InstructionsCache(const MCInstrInfo &InstrInfo,
                                     const RegisterAliasingTrackerCache &RATC)
    : … { … }

const Instruction &InstructionsCache::getInstr(unsigned Opcode) const { … }

bool RegisterOperandAssignment::
operator==(const RegisterOperandAssignment &Other) const { … }

bool AliasingRegisterOperands::
operator==(const AliasingRegisterOperands &Other) const { … }

static void
addOperandIfAlias(const MCPhysReg Reg, bool SelectDef,
                  ArrayRef<Operand> Operands,
                  SmallVectorImpl<RegisterOperandAssignment> &OperandValues) { … }

bool AliasingRegisterOperands::hasImplicitAliasing() const { … }

bool AliasingConfigurations::empty() const { … }

bool AliasingConfigurations::hasImplicitAliasing() const { … }

AliasingConfigurations::AliasingConfigurations(
    const Instruction &DefInstruction, const Instruction &UseInstruction,
    const BitVector &ForbiddenRegisters) { … }

void DumpMCOperand(const MCRegisterInfo &MCRegisterInfo, const MCOperand &Op,
                   raw_ostream &OS) { … }

void DumpMCInst(const MCRegisterInfo &MCRegisterInfo,
                const MCInstrInfo &MCInstrInfo, const MCInst &MCInst,
                raw_ostream &OS) { … }

} // namespace exegesis
} // namespace llvm