llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
# RUN:   | FileCheck -check-prefix=RV32I %s

---
name:            cttz_s32
legalized:       true
regBankSelected: true
body:             |
  bb.0.entry:
    ; RV32I-LABEL: name: cttz_s32
    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[CTZ:%[0-9]+]]:gpr = CTZ [[COPY]]
    ; RV32I-NEXT: $x10 = COPY [[CTZ]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CTTZ %0
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...