llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s

---
name:            vload_nxv1ptr
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: vload_nxv1ptr
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>))
    ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %0:_(p0) = COPY $x10
    %1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>), align 4)
    $v8 = COPY %1(<vscale x 1 x p0>)
    PseudoRET implicit $v8

...
---
name:            vload_nxv2ptr
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: vload_nxv2ptr
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>))
    ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %0:_(p0) = COPY $x10
    %1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>), align 8)
    $v8 = COPY %1(<vscale x 2 x p0>)
    PseudoRET implicit $v8

...
---
name:            vload_nxv8ptr
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: vload_nxv8ptr
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>))
    ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)
    ; CHECK-NEXT: PseudoRET implicit $v8m4
    %0:_(p0) = COPY $x10
    %1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>), align 32)
    $v8m4 = COPY %1(<vscale x 8 x p0>)
    PseudoRET implicit $v8m4

...
---
name:            vload_nxv16ptr
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: vload_nxv16ptr
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x p0>))
    ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x p0>)
    ; CHECK-NEXT: PseudoRET implicit $v8m8
    %0:_(p0) = COPY $x10
    %1:_(<vscale x 16 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 16 x p0>), align 64)
    $v8m4 = COPY %1(<vscale x 16 x p0>)
    PseudoRET implicit $v8m8

...