llvm/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
# RUN:     -verify-machineinstrs | FileCheck %s

---
name: move_src
body: |
  bb.0:
    liveins: $v8
    ; CHECK-LABEL: name: move_src
    ; CHECK: liveins: $v8
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %passthru:vr = COPY $v8
    ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
    ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
    %passthru:vr = COPY $v8
    %y:gpr = ADDI $x0, 1
    %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */
...