AArch64AddressingModes.h | Explore in Territory

//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 addressing mode implementation stuff.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H

#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/bit.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>

namespace llvm {

/// AArch64_AM - AArch64 Addressing Mode Stuff
namespace AArch64_AM {

//===----------------------------------------------------------------------===//
// Shifts
//

enum ShiftExtendType { … };

/// getShiftName - Get the string encoding for the shift type.
static inline const char *getShiftExtendName(AArch64_AM::ShiftExtendType ST) { … }

/// getShiftType - Extract the shift type.
static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { … }

/// getShiftValue - Extract the shift value.
static inline unsigned getShiftValue(unsigned Imm) { … }

/// getShifterImm - Encode the shift type and amount:
///   imm:     6-bit shift amount
///   shifter: 000 ==> lsl
///            001 ==> lsr
///            010 ==> asr
///            011 ==> ror
///            100 ==> msl
///   {8-6}  = shifter
///   {5-0}  = imm
static inline unsigned getShifterImm(AArch64_AM::ShiftExtendType ST,
                                     unsigned Imm) { … }

//===----------------------------------------------------------------------===//
// Extends
//

/// getArithShiftValue - get the arithmetic shift value.
static inline unsigned getArithShiftValue(unsigned Imm) { … }

/// getExtendType - Extract the extend type for operands of arithmetic ops.
static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { … }

static inline AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm) { … }

/// Mapping from extend bits to required operation:
///   shifter: 000 ==> uxtb
///            001 ==> uxth
///            010 ==> uxtw
///            011 ==> uxtx
///            100 ==> sxtb
///            101 ==> sxth
///            110 ==> sxtw
///            111 ==> sxtx
inline unsigned getExtendEncoding(AArch64_AM::ShiftExtendType ET) { … }

/// getArithExtendImm - Encode the extend type and shift amount for an
///                     arithmetic instruction:
///   imm:     3-bit extend amount
///   {5-3}  = shifter
///   {2-0}  = imm3
static inline unsigned getArithExtendImm(AArch64_AM::ShiftExtendType ET,
                                         unsigned Imm) { … }

/// getMemDoShift - Extract the "do shift" flag value for load/store
/// instructions.
static inline bool getMemDoShift(unsigned Imm) { … }

/// getExtendType - Extract the extend type for the offset operand of
/// loads/stores.
static inline AArch64_AM::ShiftExtendType getMemExtendType(unsigned Imm) { … }

/// getExtendImm - Encode the extend type and amount for a load/store inst:
///   doshift:     should the offset be scaled by the access size
///   shifter: 000 ==> uxtb
///            001 ==> uxth
///            010 ==> uxtw
///            011 ==> uxtx
///            100 ==> sxtb
///            101 ==> sxth
///            110 ==> sxtw
///            111 ==> sxtx
///   {3-1}  = shifter
///   {0}  = doshift
static inline unsigned getMemExtendImm(AArch64_AM::ShiftExtendType ET,
                                       bool DoShift) { … }

static inline uint64_t ror(uint64_t elt, unsigned size) { … }

/// processLogicalImmediate - Determine if an immediate value can be encoded
/// as the immediate operand of a logical instruction for the given register
/// size.  If so, return true with "encoding" set to the encoded value in
/// the form N:immr:imms.
static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
                                           uint64_t &Encoding) { … }

/// isLogicalImmediate - Return true if the immediate is valid for a logical
/// immediate instruction of the given register size. Return false otherwise.
static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) { … }

/// encodeLogicalImmediate - Return the encoded immediate value for a logical
/// immediate instruction of the given register size.
static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) { … }

/// decodeLogicalImmediate - Decode a logical immediate value in the form
/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
/// integer value it represents with regSize bits.
static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) { … }

/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
/// is a valid encoding for an integer value with regSize bits.
static inline bool isValidDecodeLogicalImmediate(uint64_t val,
                                                 unsigned regSize) { … }

//===----------------------------------------------------------------------===//
// Floating-point Immediates
//
static inline float getFPImmFloat(unsigned Imm) { … }

/// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
/// floating-point value. If the value cannot be represented as an 8-bit
/// floating-point value, then return -1.
static inline int getFP16Imm(const APInt &Imm) { … }

static inline int getFP16Imm(const APFloat &FPImm) { … }

/// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
/// floating-point value. If the value cannot be represented as an 8-bit
/// floating-point value, then return -1.
static inline int getFP32Imm(const APInt &Imm) { … }

static inline int getFP32Imm(const APFloat &FPImm) { … }

/// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
/// floating-point value. If the value cannot be represented as an 8-bit
/// floating-point value, then return -1.
static inline int getFP64Imm(const APInt &Imm) { … }

static inline int getFP64Imm(const APFloat &FPImm) { … }

//===--------------------------------------------------------------------===//
// AdvSIMD Modified Immediates
//===--------------------------------------------------------------------===//

// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
static inline bool isAdvSIMDModImmType1(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType1(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType1(uint8_t Imm) { … }

// 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
static inline bool isAdvSIMDModImmType2(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType2(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType2(uint8_t Imm) { … }

// 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
static inline bool isAdvSIMDModImmType3(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType3(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType3(uint8_t Imm) { … }

// abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
static inline bool isAdvSIMDModImmType4(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType4(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType4(uint8_t Imm) { … }

// 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
static inline bool isAdvSIMDModImmType5(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType5(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType5(uint8_t Imm) { … }

// abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
static inline bool isAdvSIMDModImmType6(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType6(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType6(uint8_t Imm) { … }

// 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
static inline bool isAdvSIMDModImmType7(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType7(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType7(uint8_t Imm) { … }

// 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
static inline bool isAdvSIMDModImmType8(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType8(uint8_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType8(uint64_t Imm) { … }

// abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
static inline bool isAdvSIMDModImmType9(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType9(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType9(uint8_t Imm) { … }

// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
// cmode: 1110, op: 1
static inline bool isAdvSIMDModImmType10(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType10(uint8_t Imm) { … }

// aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
static inline bool isAdvSIMDModImmType11(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType11(uint8_t Imm) { … }

// aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
static inline bool isAdvSIMDModImmType12(uint64_t Imm) { … }

static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) { … }

static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) { … }

/// Returns true if Imm is the concatenation of a repeating pattern of type T.
template <typename T>
static inline bool isSVEMaskOfIdenticalElements(int64_t Imm) { … }

/// Returns true if Imm is valid for CPY/DUP.
template <typename T>
static inline bool isSVECpyImm(int64_t Imm) { … }

/// Returns true if Imm is valid for ADD/SUB.
template <typename T>
static inline bool isSVEAddSubImm(int64_t Imm) { … }

/// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
static inline bool isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) { … }

inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { … }

inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { … }

inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { … }

inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { … }

} // end namespace AArch64_AM

} // end namespace llvm

#endif
llvm/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
