AArch64AsmParser.cpp | Explore in Territory

//==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "AArch64InstrInfo.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "MCTargetDesc/AArch64InstPrinter.h"
#include "MCTargetDesc/AArch64MCExpr.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "MCTargetDesc/AArch64TargetStreamer.h"
#include "TargetInfo/AArch64TargetInfo.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCLinkerOptimizationHint.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/MC/MCValue.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include <cassert>
#include <cctype>
#include <cstdint>
#include <cstdio>
#include <optional>
#include <string>
#include <tuple>
#include <utility>
#include <vector>

usingnamespacellvm;

namespace {

enum class RegKind { … };

enum class MatrixKind { … };

enum RegConstraintEqualityTy { … };

class AArch64AsmParser : public MCTargetAsmParser { … };

/// AArch64Operand - Instances of this class represent a parsed AArch64 machine
/// instruction.
class AArch64Operand : public MCParsedAsmOperand { … };

} // end anonymous namespace.

void AArch64Operand::print(raw_ostream &OS) const { … }

/// @name Auto-generated Match Functions
/// {

static MCRegister MatchRegisterName(StringRef Name);

/// }

static unsigned MatchNeonVectorRegName(StringRef Name) { … }

/// Returns an optional pair of (#elements, element-width) if Suffix
/// is a valid vector kind. Where the number of elements in a vector
/// or the vector width is implicit or explicitly unknown (but still a
/// valid suffix kind), 0 is used.
static std::optional<std::pair<int, int>> parseVectorKind(StringRef Suffix,
                                                          RegKind VectorKind) { … }

static bool isValidVectorKind(StringRef Suffix, RegKind VectorKind) { … }

static unsigned matchSVEDataVectorRegName(StringRef Name) { … }

static unsigned matchSVEPredicateVectorRegName(StringRef Name) { … }

static unsigned matchSVEPredicateAsCounterRegName(StringRef Name) { … }

static unsigned matchMatrixTileListRegName(StringRef Name) { … }

static unsigned matchMatrixRegName(StringRef Name) { … }

bool AArch64AsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
                                     SMLoc &EndLoc) { … }

ParseStatus AArch64AsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
                                               SMLoc &EndLoc) { … }

// Matches a register name or register alias previously defined by '.req'
unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
                                                  RegKind Kind) { … }

unsigned AArch64AsmParser::getNumRegsForRegKind(RegKind K) { … }

/// tryParseScalarRegister - Try to parse a register name. The token must be an
/// Identifier when called, and if it is a register name the token is eaten and
/// the register is added to the operand list.
ParseStatus AArch64AsmParser::tryParseScalarRegister(MCRegister &RegNum) { … }

/// tryParseSysCROperand - Try to parse a system instruction CR operand name.
ParseStatus AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) { … }

// Either an identifier for named values or a 6-bit immediate.
ParseStatus AArch64AsmParser::tryParseRPRFMOperand(OperandVector &Operands) { … }

/// tryParsePrefetch - Try to parse a prefetch operand.
template <bool IsSVEPrefetch>
ParseStatus AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) { … }

/// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command
ParseStatus AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseSyspXzrPair(OperandVector &Operands) { … }

/// tryParseBTIHint - Try to parse a BTI operand, mapped to Hint command
ParseStatus AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) { … }

/// tryParseAdrpLabel - Parse and validate a source label for the ADRP
/// instruction.
ParseStatus AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) { … }

/// tryParseAdrLabel - Parse and validate a source label for the ADR
/// instruction.
ParseStatus AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) { … }

/// tryParseFPImm - A floating point immediate expression operand.
template <bool AddFPZeroAsLiteral>
ParseStatus AArch64AsmParser::tryParseFPImm(OperandVector &Operands) { … }

/// tryParseImmWithOptionalShift - Parse immediate operand, optionally with
/// a shift suffix, for example '#1, lsl #12'.
ParseStatus
AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) { … }

/// parseCondCodeString - Parse a Condition Code string, optionally returning a
/// suggestion to help common typos.
AArch64CC::CondCode
AArch64AsmParser::parseCondCodeString(StringRef Cond, std::string &Suggestion) { … }

/// parseCondCode - Parse a Condition Code operand.
bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
                                     bool invertCondCode) { … }

ParseStatus AArch64AsmParser::tryParseSVCR(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) { … }

/// tryParseOptionalShift - Some operands take an optional shift argument. Parse
/// them if present.
ParseStatus
AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) { … }

static const struct Extension { … } ExtensionMap[] = …;

static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) { … }

void AArch64AsmParser::createSysAlias(uint16_t Encoding, OperandVector &Operands,
                                      SMLoc S) { … }

/// parseSysAlias - The IC, DC, AT, and TLBI instructions are simple aliases for
/// the SYS instruction. Parse them specially so that we create a SYS MCInst.
bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
                                   OperandVector &Operands) { … }

/// parseSyspAlias - The TLBIP instructions are simple aliases for
/// the SYSP instruction. Parse them specially so that we create a SYSP MCInst.
bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
                                      OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) { … }

ParseStatus
AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseSysReg(OperandVector &Operands) { … }

/// tryParseNeonVectorRegister - Parse a vector register operand.
bool AArch64AsmParser::tryParseNeonVectorRegister(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) { … }

// tryParseVectorRegister - Try to parse a vector register name with
// optional kind specifier. If it is a register specifier, eat the token
// and return it.
ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg,
                                                     StringRef &Kind,
                                                     RegKind MatchKind) { … }

ParseStatus AArch64AsmParser::tryParseSVEPredicateOrPredicateAsCounterVector(
    OperandVector &Operands) { … }

/// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
template <RegKind RK>
ParseStatus
AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) { … }

/// parseRegister - Parse a register operand.
bool AArch64AsmParser::parseRegister(OperandVector &Operands) { … }

bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) { … }

ParseStatus AArch64AsmParser::tryParseMatrixTileList(OperandVector &Operands) { … }

template <RegKind VectorKind>
ParseStatus AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
                                                 bool ExpectMatch) { … }

/// parseNeonVectorList - Parse a vector list operand for AdvSIMD instructions.
bool AArch64AsmParser::parseNeonVectorList(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseZTOperand(OperandVector &Operands) { … }

template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy>
ParseStatus AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) { … }

bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) { … }

bool AArch64AsmParser::parseOptionalVGOperand(OperandVector &Operands,
                                              StringRef &VecGroup) { … }

bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) { … }

/// parseOperand - Parse a arm instruction operand.  For now this parses the
/// operand regardless of the mnemonic.
bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
                                  bool invertCondCode) { … }

bool AArch64AsmParser::parseImmExpr(int64_t &Out) { … }

bool AArch64AsmParser::parseComma() { … }

bool AArch64AsmParser::parseRegisterInRange(unsigned &Out, unsigned Base,
                                            unsigned First, unsigned Last) { … }

bool AArch64AsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
                                    const MCParsedAsmOperand &Op2) const { … }

/// Parse an AArch64 instruction mnemonic followed by its operands.
bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
                                        StringRef Name, SMLoc NameLoc,
                                        OperandVector &Operands) { … }

static inline bool isMatchingOrAlias(MCRegister ZReg, MCRegister Reg) { … }

// FIXME: This entire function is a giant hack to provide us with decent
// operand range validation/diagnostics until TableGen/MC can be extended
// to support autogeneration of this kind of validation.
bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
                                           SmallVectorImpl<SMLoc> &Loc) { … }

static std::string AArch64MnemonicSpellCheck(StringRef S,
                                             const FeatureBitset &FBS,
                                             unsigned VariantID = 0);

bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
                                      uint64_t ErrorInfo,
                                      OperandVector &Operands) { … }

static const char *getSubtargetFeatureName(uint64_t Val);

bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                               OperandVector &Operands,
                                               MCStreamer &Out,
                                               uint64_t &ErrorInfo,
                                               bool MatchingInlineAsm) { … }

/// ParseDirective parses the arm specific directives
bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) { … }

static void ExpandCryptoAEK(const AArch64::ArchInfo &ArchInfo,
                            SmallVector<StringRef, 4> &RequestedExtensions) { … }

static SMLoc incrementLoc(SMLoc L, int Offset) { … }

/// parseDirectiveArch
///   ::= .arch token
bool AArch64AsmParser::parseDirectiveArch(SMLoc L) { … }

/// parseDirectiveArchExtension
///   ::= .arch_extension [no]feature
bool AArch64AsmParser::parseDirectiveArchExtension(SMLoc L) { … }

/// parseDirectiveCPU
///   ::= .cpu id
bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) { … }

/// parseDirectiveInst
///  ::= .inst opcode [, ...]
bool AArch64AsmParser::parseDirectiveInst(SMLoc Loc) { … }

// parseDirectiveTLSDescCall:
//   ::= .tlsdesccall symbol
bool AArch64AsmParser::parseDirectiveTLSDescCall(SMLoc L) { … }

/// ::= .loh <lohName | lohId> label1, ..., labelN
/// The number of arguments depends on the loh identifier.
bool AArch64AsmParser::parseDirectiveLOH(StringRef IDVal, SMLoc Loc) { … }

/// parseDirectiveLtorg
///  ::= .ltorg | .pool
bool AArch64AsmParser::parseDirectiveLtorg(SMLoc L) { … }

/// parseDirectiveReq
///  ::= name .req registername
bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { … }

/// parseDirectiveUneq
///  ::= .unreq registername
bool AArch64AsmParser::parseDirectiveUnreq(SMLoc L) { … }

bool AArch64AsmParser::parseDirectiveCFINegateRAState() { … }

/// parseDirectiveCFIBKeyFrame
/// ::= .cfi_b_key
bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() { … }

/// parseDirectiveCFIMTETaggedFrame
/// ::= .cfi_mte_tagged_frame
bool AArch64AsmParser::parseDirectiveCFIMTETaggedFrame() { … }

/// parseDirectiveVariantPCS
/// ::= .variant_pcs symbolname
bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) { … }

/// parseDirectiveSEHAllocStack
/// ::= .seh_stackalloc
bool AArch64AsmParser::parseDirectiveSEHAllocStack(SMLoc L) { … }

/// parseDirectiveSEHPrologEnd
/// ::= .seh_endprologue
bool AArch64AsmParser::parseDirectiveSEHPrologEnd(SMLoc L) { … }

/// parseDirectiveSEHSaveR19R20X
/// ::= .seh_save_r19r20_x
bool AArch64AsmParser::parseDirectiveSEHSaveR19R20X(SMLoc L) { … }

/// parseDirectiveSEHSaveFPLR
/// ::= .seh_save_fplr
bool AArch64AsmParser::parseDirectiveSEHSaveFPLR(SMLoc L) { … }

/// parseDirectiveSEHSaveFPLRX
/// ::= .seh_save_fplr_x
bool AArch64AsmParser::parseDirectiveSEHSaveFPLRX(SMLoc L) { … }

/// parseDirectiveSEHSaveReg
/// ::= .seh_save_reg
bool AArch64AsmParser::parseDirectiveSEHSaveReg(SMLoc L) { … }

/// parseDirectiveSEHSaveRegX
/// ::= .seh_save_reg_x
bool AArch64AsmParser::parseDirectiveSEHSaveRegX(SMLoc L) { … }

/// parseDirectiveSEHSaveRegP
/// ::= .seh_save_regp
bool AArch64AsmParser::parseDirectiveSEHSaveRegP(SMLoc L) { … }

/// parseDirectiveSEHSaveRegPX
/// ::= .seh_save_regp_x
bool AArch64AsmParser::parseDirectiveSEHSaveRegPX(SMLoc L) { … }

/// parseDirectiveSEHSaveLRPair
/// ::= .seh_save_lrpair
bool AArch64AsmParser::parseDirectiveSEHSaveLRPair(SMLoc L) { … }

/// parseDirectiveSEHSaveFReg
/// ::= .seh_save_freg
bool AArch64AsmParser::parseDirectiveSEHSaveFReg(SMLoc L) { … }

/// parseDirectiveSEHSaveFRegX
/// ::= .seh_save_freg_x
bool AArch64AsmParser::parseDirectiveSEHSaveFRegX(SMLoc L) { … }

/// parseDirectiveSEHSaveFRegP
/// ::= .seh_save_fregp
bool AArch64AsmParser::parseDirectiveSEHSaveFRegP(SMLoc L) { … }

/// parseDirectiveSEHSaveFRegPX
/// ::= .seh_save_fregp_x
bool AArch64AsmParser::parseDirectiveSEHSaveFRegPX(SMLoc L) { … }

/// parseDirectiveSEHSetFP
/// ::= .seh_set_fp
bool AArch64AsmParser::parseDirectiveSEHSetFP(SMLoc L) { … }

/// parseDirectiveSEHAddFP
/// ::= .seh_add_fp
bool AArch64AsmParser::parseDirectiveSEHAddFP(SMLoc L) { … }

/// parseDirectiveSEHNop
/// ::= .seh_nop
bool AArch64AsmParser::parseDirectiveSEHNop(SMLoc L) { … }

/// parseDirectiveSEHSaveNext
/// ::= .seh_save_next
bool AArch64AsmParser::parseDirectiveSEHSaveNext(SMLoc L) { … }

/// parseDirectiveSEHEpilogStart
/// ::= .seh_startepilogue
bool AArch64AsmParser::parseDirectiveSEHEpilogStart(SMLoc L) { … }

/// parseDirectiveSEHEpilogEnd
/// ::= .seh_endepilogue
bool AArch64AsmParser::parseDirectiveSEHEpilogEnd(SMLoc L) { … }

/// parseDirectiveSEHTrapFrame
/// ::= .seh_trap_frame
bool AArch64AsmParser::parseDirectiveSEHTrapFrame(SMLoc L) { … }

/// parseDirectiveSEHMachineFrame
/// ::= .seh_pushframe
bool AArch64AsmParser::parseDirectiveSEHMachineFrame(SMLoc L) { … }

/// parseDirectiveSEHContext
/// ::= .seh_context
bool AArch64AsmParser::parseDirectiveSEHContext(SMLoc L) { … }

/// parseDirectiveSEHECContext
/// ::= .seh_ec_context
bool AArch64AsmParser::parseDirectiveSEHECContext(SMLoc L) { … }

/// parseDirectiveSEHClearUnwoundToCall
/// ::= .seh_clear_unwound_to_call
bool AArch64AsmParser::parseDirectiveSEHClearUnwoundToCall(SMLoc L) { … }

/// parseDirectiveSEHPACSignLR
/// ::= .seh_pac_sign_lr
bool AArch64AsmParser::parseDirectiveSEHPACSignLR(SMLoc L) { … }

/// parseDirectiveSEHSaveAnyReg
/// ::= .seh_save_any_reg
/// ::= .seh_save_any_reg_p
/// ::= .seh_save_any_reg_x
/// ::= .seh_save_any_reg_px
bool AArch64AsmParser::parseDirectiveSEHSaveAnyReg(SMLoc L, bool Paired,
                                                   bool Writeback) { … }

bool AArch64AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) { … }

///  parseAuthExpr
///  ::= _sym@AUTH(ib,123[,addr])
///  ::= (_sym + 5)@AUTH(ib,123[,addr])
///  ::= (_sym - 5)@AUTH(ib,123[,addr])
bool AArch64AsmParser::parseAuthExpr(const MCExpr *&Res, SMLoc &EndLoc) { … }

bool
AArch64AsmParser::classifySymbolRef(const MCExpr *Expr,
                                    AArch64MCExpr::VariantKind &ELFRefKind,
                                    MCSymbolRefExpr::VariantKind &DarwinRefKind,
                                    int64_t &Addend) { … }

/// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64AsmParser() { … }

#define GET_REGISTER_MATCHER
#define GET_SUBTARGET_FEATURE_NAME
#define GET_MATCHER_IMPLEMENTATION
#define GET_MNEMONIC_SPELL_CHECKER
#include "AArch64GenAsmMatcher.inc"

// Define this matcher function after the auto-generated include so we
// have the match class enum definitions.
unsigned AArch64AsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
                                                      unsigned Kind) { … }

ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) { … }

template <bool ParseShiftExtend, bool ParseSuffix>
ParseStatus AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) { … }

ParseStatus
AArch64AsmParser::tryParseSVEVecLenSpecifier(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) { … }

ParseStatus AArch64AsmParser::tryParseImmRange(OperandVector &Operands) { … }
llvm/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
