llvm/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp

//===- GCNMinRegStrategy.cpp ----------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file defines and implements the class GCNMinRegScheduler, which
/// implements an experimental, simple scheduler whose main goal is to learn
/// ways about consuming less possible registers for a region.
///
//===----------------------------------------------------------------------===//

#include "llvm/CodeGen/ScheduleDAG.h"
usingnamespacellvm;

#define DEBUG_TYPE …

namespace {

class GCNMinRegScheduler { … };

} // end anonymous namespace

void GCNMinRegScheduler::initNumPreds(const decltype(ScheduleDAG::SUnits) &SUnits) { … }

int GCNMinRegScheduler::getReadySuccessors(const SUnit *SU) const { … }

int GCNMinRegScheduler::getNotReadySuccessors(const SUnit *SU) const { … }

template <typename Calc>
unsigned GCNMinRegScheduler::findMax(unsigned Num, Calc C) { … }

GCNMinRegScheduler::Candidate* GCNMinRegScheduler::pickCandidate() { … }

void GCNMinRegScheduler::bumpPredsPriority(const SUnit *SchedSU, int Priority) { … }

void GCNMinRegScheduler::releaseSuccessors(const SUnit* SU, int Priority) { … }

std::vector<const SUnit*>
GCNMinRegScheduler::schedule(ArrayRef<const SUnit*> TopRoots,
                             const ScheduleDAG &DAG) { … }

namespace llvm {

std::vector<const SUnit*> makeMinRegSchedule(ArrayRef<const SUnit*> TopRoots,
                                             const ScheduleDAG &DAG) { … }

} // end namespace llvm