//===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // //===----------------------------------------------------------------------===// // /// \file /// /// This file contains definition for AMDGPU ISA disassembler // //===----------------------------------------------------------------------===// // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? #include "Disassembler/AMDGPUDisassembler.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "SIDefines.h" #include "SIRegisterInfo.h" #include "TargetInfo/AMDGPUTargetInfo.h" #include "Utils/AMDGPUAsmUtils.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm-c/DisassemblerTypes.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDecoderOps.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/AMDHSAKernelDescriptor.h" usingnamespacellvm; #define DEBUG_TYPE … #define SGPR_MAX … DecodeStatus; static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI, MCContext &Ctx) { … } AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII) : … { … } void AMDGPUDisassembler::setABIVersion(unsigned Version) { … } inline static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand& Opnd) { … } static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx) { … } static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) { … } static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) { … } static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder) { … } static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder) { … } static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder) { … } #define DECODE_OPERAND(StaticDecoderName, DecoderName) … // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is // number of register. Used by VGPR only and AGPR only operands. #define DECODE_OPERAND_REG_8(RegClass) … #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ ImmWidth) … static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, AMDGPUDisassembler::OpWidthTy OpWidth, unsigned Imm, unsigned EncImm, bool MandatoryLiteral, unsigned ImmWidth, AMDGPU::OperandSemantics Sema, const MCDisassembler *Decoder) { … } // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to // get register class. Used by SGPR only operands. #define DECODE_OPERAND_REG_7(RegClass, OpWidth) … // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. // Used by AV_ register classes (AGPR or VGPR only register operands). template <AMDGPUDisassembler::OpWidthTy OpWidth> static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } // Decoder for Src(9-bit encoding) registers only. template <AMDGPUDisassembler::OpWidthTy OpWidth> static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers // only. template <AMDGPUDisassembler::OpWidthTy OpWidth> static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding // Imm{9} is acc, registers only. template <AMDGPUDisassembler::OpWidthTy OpWidth> static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be // register from RegClass or immediate. Registers that don't belong to RegClass // will be decoded and InstPrinter will report warning. Immediate will be // decoded into constant of size ImmWidth, should match width of immediate used // by OperandType (important for floating point types). template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics> static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) // and decode using 'enum10' from decodeSrcOp. template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics> static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics> static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' // when RegisterClass is used as an operand. Most often used for destination // operands. DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_7(…) … DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) DECODE_OPERAND_REG_8(…) static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, const MCDisassembler *Decoder) { … } static DecodeStatus DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, const MCDisassembler *Decoder) { … } template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics> static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, const MCDisassembler *Decoder) { … } template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics> static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, const MCDisassembler *Decoder) { … } static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) { … } static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder) { … } static bool IsAGPROperand(const MCInst &Inst, int OpIdx, const MCRegisterInfo *MRI) { … } static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder) { … } template <AMDGPUDisassembler::OpWidthTy Opw> static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) { … } #define DECODE_SDWA(DecName) … DECODE_SDWA(…) DECODE_SDWA(…) DECODE_SDWA(…) static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, const MCDisassembler *Decoder) { … } #include "AMDGPUGenDisassemblerTables.inc" //===----------------------------------------------------------------------===// // //===----------------------------------------------------------------------===// template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { … } static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { … } DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes_, uint64_t Address, raw_ostream &CS) const { … } void AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { … } void AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { … } void AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { … } struct VOPModifiers { … }; // Reconstruct values of VOP3/VOP3P operands such as op_sel. // Note that these values do not affect disassembler output, // so this is only necessary for consistency with src_modifiers. static VOPModifiers collectVOPModifiers(const MCInst &MI, bool IsVOP3P = false) { … } // Instructions decode the op_sel/suffix bits into the src_modifier // operands. Copy those bits into the src operands for true16 VGPRs. void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const { … } // MAC opcodes have special old and src2 operands. // src2 is tied to dst, while old is not tied (but assumed to be). bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { … } // Create dummy old operand and insert dummy unused src2_modifiers void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { … } void AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { … } void AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { … } // Note that before gfx10, the MIMG encoding provided no information about // VADDR size. Consequently, decoded instructions always show address as if it // has 1 dword, which could be not really so. void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { … } // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen // decoder only adds to src_modifiers, so manually add the bits to the other // operands. void AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { … } // Create dummy old operand and insert optional operands void AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { … } void AMDGPUDisassembler::convertFMAanyK(MCInst &MI, int ImmLitIdx) const { … } const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { … } inline MCOperand AMDGPUDisassembler::errOperand(unsigned V, const Twine& ErrMsg) const { … } inline MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { … } inline MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, unsigned Val) const { … } inline MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, unsigned Val) const { … } MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, bool IsHi) const { … } // Decode Literals for insts which always have a literal in the encoding MCOperand AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { … } MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { … } static int64_t getInlineImmVal32(unsigned Imm) { … } static int64_t getInlineImmVal64(unsigned Imm) { … } static int64_t getInlineImmValF16(unsigned Imm) { … } static int64_t getInlineImmValBF16(unsigned Imm) { … } static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) { … } MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm, AMDGPU::OperandSemantics Sema) { … } unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { … } unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { … } unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { … } unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { … } int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) const { … } MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) const { … } // Bit 0 of DstY isn't stored in the instruction, because it's always the // opposite of bit 0 of DstX. MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) const { … } MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const { … } MCOperand AMDGPUDisassembler::decodeVersionImm(unsigned Imm) const { … } bool AMDGPUDisassembler::isVI() const { … } bool AMDGPUDisassembler::isGFX9() const { … } bool AMDGPUDisassembler::isGFX90A() const { … } bool AMDGPUDisassembler::isGFX9Plus() const { … } bool AMDGPUDisassembler::isGFX10() const { … } bool AMDGPUDisassembler::isGFX10Plus() const { … } bool AMDGPUDisassembler::isGFX11() const { … } bool AMDGPUDisassembler::isGFX11Plus() const { … } bool AMDGPUDisassembler::isGFX12() const { … } bool AMDGPUDisassembler::isGFX12Plus() const { … } bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { … } bool AMDGPUDisassembler::hasKernargPreload() const { … } //===----------------------------------------------------------------------===// // AMDGPU specific symbol handling //===----------------------------------------------------------------------===// /// Print a string describing the reserved bit range specified by Mask with /// offset BaseBytes for use in error comments. Mask is a single continuous /// range of 1s surrounded by zeros. The format here is meant to align with the /// tables that describe these bits in llvm.org/docs/AMDGPUUsage.html. static SmallString<32> getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes) { … } #define GET_FIELD … #define PRINT_DIRECTIVE … #define PRINT_PSEUDO_DIRECTIVE_COMMENT … #define CHECK_RESERVED_BITS_IMPL … #define CHECK_RESERVED_BITS … #define CHECK_RESERVED_BITS_MSG … #define CHECK_RESERVED_BITS_DESC … #define CHECK_RESERVED_BITS_DESC_MSG … // NOLINTNEXTLINE(readability-identifier-naming) Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { … } // NOLINTNEXTLINE(readability-identifier-naming) Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { … } // NOLINTNEXTLINE(readability-identifier-naming) Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { … } #undef PRINT_PSEUDO_DIRECTIVE_COMMENT #undef PRINT_DIRECTIVE #undef GET_FIELD #undef CHECK_RESERVED_BITS_IMPL #undef CHECK_RESERVED_BITS #undef CHECK_RESERVED_BITS_MSG #undef CHECK_RESERVED_BITS_DESC #undef CHECK_RESERVED_BITS_DESC_MSG /// Create an error object to return from onSymbolStart for reserved kernel /// descriptor bits being set. static Error createReservedKDBitsError(uint32_t Mask, unsigned BaseBytes, const char *Msg = "") { … } /// Create an error object to return from onSymbolStart for reserved kernel /// descriptor bytes being set. static Error createReservedKDBytesError(unsigned BaseInBytes, unsigned WidthInBytes) { … } Expected<bool> AMDGPUDisassembler::decodeKernelDescriptorDirective( DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, raw_string_ostream &KdStream) const { … } Expected<bool> AMDGPUDisassembler::decodeKernelDescriptor( StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { … } Expected<bool> AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address) const { … } const MCExpr *AMDGPUDisassembler::createConstantSymbolExpr(StringRef Id, int64_t Val) { … } //===----------------------------------------------------------------------===// // AMDGPUSymbolizer //===----------------------------------------------------------------------===// // Try to find symbol name for specified label bool AMDGPUSymbolizer::tryAddingSymbolicOperand( MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, uint64_t /*OpSize*/, uint64_t /*InstSize*/) { … } void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) { … } //===----------------------------------------------------------------------===// // Initialization //===----------------------------------------------------------------------===// static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, LLVMOpInfoCallback /*GetOpInfo*/, LLVMSymbolLookupCallback /*SymbolLookUp*/, void *DisInfo, MCContext *Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo) { … } static MCDisassembler *createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { … } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { … }
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