AMDGPUBaseInfo.cpp | Explore in Territory

//===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "AMDGPUBaseInfo.h"
#include "AMDGPU.h"
#include "AMDGPUAsmUtils.h"
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "Utils/AMDKernelCodeTUtils.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/TargetParser/TargetParser.h"
#include <optional>

#define GET_INSTRINFO_NAMED_OPS
#define GET_INSTRMAP_INFO
#include "AMDGPUGenInstrInfo.inc"

static llvm::cl::opt<unsigned> DefaultAMDHSACodeObjectVersion(
    "amdhsa-code-object-version", llvm::cl::Hidden,
    llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5),
    llvm::cl::desc("Set default AMDHSA Code Object Version (module flag "
                   "or asm directive still take priority if present)"));

namespace {

/// \returns Bit mask for given bit \p Shift and bit \p Width.
unsigned getBitMask(unsigned Shift, unsigned Width) { … }

/// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
///
/// \returns Packed \p Dst.
unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) { … }

/// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
///
/// \returns Unpacked bits.
unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) { … }

/// \returns Vmcnt bit shift (lower bits).
unsigned getVmcntBitShiftLo(unsigned VersionMajor) { … }

/// \returns Vmcnt bit width (lower bits).
unsigned getVmcntBitWidthLo(unsigned VersionMajor) { … }

/// \returns Expcnt bit shift.
unsigned getExpcntBitShift(unsigned VersionMajor) { … }

/// \returns Expcnt bit width.
unsigned getExpcntBitWidth(unsigned VersionMajor) { … }

/// \returns Lgkmcnt bit shift.
unsigned getLgkmcntBitShift(unsigned VersionMajor) { … }

/// \returns Lgkmcnt bit width.
unsigned getLgkmcntBitWidth(unsigned VersionMajor) { … }

/// \returns Vmcnt bit shift (higher bits).
unsigned getVmcntBitShiftHi(unsigned VersionMajor) { … }

/// \returns Vmcnt bit width (higher bits).
unsigned getVmcntBitWidthHi(unsigned VersionMajor) { … }

/// \returns Loadcnt bit width
unsigned getLoadcntBitWidth(unsigned VersionMajor) { … }

/// \returns Samplecnt bit width.
unsigned getSamplecntBitWidth(unsigned VersionMajor) { … }

/// \returns Bvhcnt bit width.
unsigned getBvhcntBitWidth(unsigned VersionMajor) { … }

/// \returns Dscnt bit width.
unsigned getDscntBitWidth(unsigned VersionMajor) { … }

/// \returns Dscnt bit shift in combined S_WAIT instructions.
unsigned getDscntBitShift(unsigned VersionMajor) { … }

/// \returns Storecnt or Vscnt bit width, depending on VersionMajor.
unsigned getStorecntBitWidth(unsigned VersionMajor) { … }

/// \returns Kmcnt bit width.
unsigned getKmcntBitWidth(unsigned VersionMajor) { … }

/// \returns shift for Loadcnt/Storecnt in combined S_WAIT instructions.
unsigned getLoadcntStorecntBitShift(unsigned VersionMajor) { … }

/// \returns VmVsrc bit width
inline unsigned getVmVsrcBitWidth() { … }

/// \returns VmVsrc bit shift
inline unsigned getVmVsrcBitShift() { … }

/// \returns VaVdst bit width
inline unsigned getVaVdstBitWidth() { … }

/// \returns VaVdst bit shift
inline unsigned getVaVdstBitShift() { … }

/// \returns SaSdst bit width
inline unsigned getSaSdstBitWidth() { … }

/// \returns SaSdst bit shift
inline unsigned getSaSdstBitShift() { … }

} // end anonymous namespace

namespace llvm {

namespace AMDGPU {

/// \returns true if the target supports signed immediate offset for SMRD
/// instructions.
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST) { … }

/// \returns True if \p STI is AMDHSA.
bool isHsaAbi(const MCSubtargetInfo &STI) { … }

unsigned getAMDHSACodeObjectVersion(const Module &M) { … }

unsigned getDefaultAMDHSACodeObjectVersion() { … }

unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion) { … }

uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion) { … }

unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion) { … }


// FIXME: All such magic numbers about the ABI should be in a
// central TD file.
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion) { … }

unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion) { … }

unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion) { … }

#define GET_MIMGBaseOpcodesTable_IMPL
#define GET_MIMGDimInfoTable_IMPL
#define GET_MIMGInfoTable_IMPL
#define GET_MIMGLZMappingTable_IMPL
#define GET_MIMGMIPMappingTable_IMPL
#define GET_MIMGBiasMappingTable_IMPL
#define GET_MIMGOffsetMappingTable_IMPL
#define GET_MIMGG16MappingTable_IMPL
#define GET_MAIInstInfoTable_IMPL
#include "AMDGPUGenSearchableTables.inc"

int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
                  unsigned VDataDwords, unsigned VAddrDwords) { … }

const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) { … }

int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) { … }

unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
                           const MIMGDimInfo *Dim, bool IsA16,
                           bool IsG16Supported) { … }

struct MUBUFInfo { … };

struct MTBUFInfo { … };

struct SMInfo { … };

struct VOPInfo { … };

struct VOPC64DPPInfo { … };

struct VOPCDPPAsmOnlyInfo { … };

struct VOP3CDPPAsmOnlyInfo { … };

struct VOPDComponentInfo { … };

struct VOPDInfo { … };

struct VOPTrue16Info { … };

struct FP8DstByteSelInfo { … };

#define GET_FP8DstByteSelTable_DECL
#define GET_FP8DstByteSelTable_IMPL
#define GET_MTBUFInfoTable_DECL
#define GET_MTBUFInfoTable_IMPL
#define GET_MUBUFInfoTable_DECL
#define GET_MUBUFInfoTable_IMPL
#define GET_SMInfoTable_DECL
#define GET_SMInfoTable_IMPL
#define GET_VOP1InfoTable_DECL
#define GET_VOP1InfoTable_IMPL
#define GET_VOP2InfoTable_DECL
#define GET_VOP2InfoTable_IMPL
#define GET_VOP3InfoTable_DECL
#define GET_VOP3InfoTable_IMPL
#define GET_VOPC64DPPTable_DECL
#define GET_VOPC64DPPTable_IMPL
#define GET_VOPC64DPP8Table_DECL
#define GET_VOPC64DPP8Table_IMPL
#define GET_VOPCAsmOnlyInfoTable_DECL
#define GET_VOPCAsmOnlyInfoTable_IMPL
#define GET_VOP3CAsmOnlyInfoTable_DECL
#define GET_VOP3CAsmOnlyInfoTable_IMPL
#define GET_VOPDComponentTable_DECL
#define GET_VOPDComponentTable_IMPL
#define GET_VOPDPairs_DECL
#define GET_VOPDPairs_IMPL
#define GET_VOPTrue16Table_DECL
#define GET_VOPTrue16Table_IMPL
#define GET_WMMAOpcode2AddrMappingTable_DECL
#define GET_WMMAOpcode2AddrMappingTable_IMPL
#define GET_WMMAOpcode3AddrMappingTable_DECL
#define GET_WMMAOpcode3AddrMappingTable_IMPL
#include "AMDGPUGenSearchableTables.inc"

int getMTBUFBaseOpcode(unsigned Opc) { … }

int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { … }

int getMTBUFElements(unsigned Opc) { … }

bool getMTBUFHasVAddr(unsigned Opc) { … }

bool getMTBUFHasSrsrc(unsigned Opc) { … }

bool getMTBUFHasSoffset(unsigned Opc) { … }

int getMUBUFBaseOpcode(unsigned Opc) { … }

int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { … }

int getMUBUFElements(unsigned Opc) { … }

bool getMUBUFHasVAddr(unsigned Opc) { … }

bool getMUBUFHasSrsrc(unsigned Opc) { … }

bool getMUBUFHasSoffset(unsigned Opc) { … }

bool getMUBUFIsBufferInv(unsigned Opc) { … }

bool getMUBUFTfe(unsigned Opc) { … }

bool getSMEMIsBuffer(unsigned Opc) { … }

bool getVOP1IsSingle(unsigned Opc) { … }

bool getVOP2IsSingle(unsigned Opc) { … }

bool getVOP3IsSingle(unsigned Opc) { … }

bool isVOPC64DPP(unsigned Opc) { … }

bool isVOPCAsmOnly(unsigned Opc) { … }

bool getMAIIsDGEMM(unsigned Opc) { … }

bool getMAIIsGFX940XDL(unsigned Opc) { … }

unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST) { … }

CanBeVOPD getCanBeVOPD(unsigned Opc) { … }

unsigned getVOPDOpcode(unsigned Opc) { … }

bool isVOPD(unsigned Opc) { … }

bool isMAC(unsigned Opc) { … }

bool isPermlane16(unsigned Opc) { … }

bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc) { … }

bool isGenericAtomic(unsigned Opc) { … }

bool isTrue16Inst(unsigned Opc) { … }

bool isFP8DstSelInst(unsigned Opc) { … }

unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) { … }

unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc) { … }

// Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
// header files, so we need to wrap it in a function that takes unsigned
// instead.
int getMCOpcode(uint16_t Opcode, unsigned Gen) { … }

int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily) { … }

std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode) { … }

namespace VOPD {

ComponentProps::ComponentProps(const MCInstrDesc &OpDesc) { … }

unsigned ComponentInfo::getIndexInParsedOperands(unsigned CompOprIdx) const { … }

std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
    std::function<unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc) const { … }

// Return an array of VGPR registers [DST,SRC0,SRC1,SRC2] used
// by the specified component. If an operand is unused
// or is not a VGPR, the corresponding value is 0.
//
// GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
// for the specified component and MC operand. The callback must return 0
// if the operand is not a register or not a VGPR.
InstInfo::RegIndices InstInfo::getRegIndices(
    unsigned CompIdx,
    std::function<unsigned(unsigned, unsigned)> GetRegIdx) const { … }

} // namespace VOPD

VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY) { … }

VOPD::InstInfo getVOPDInstInfo(unsigned VOPDOpcode,
                               const MCInstrInfo *InstrInfo) { … }

namespace IsaInfo {

AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI)
    : … { … }

void AMDGPUTargetID::setTargetIDFromFeaturesString(StringRef FS) { … }

static TargetIDSetting
getTargetIDSettingFromFeatureString(StringRef FeatureString) { … }

void AMDGPUTargetID::setTargetIDFromTargetIDStream(StringRef TargetID) { … }

std::string AMDGPUTargetID::toString() const { … }

unsigned getWavefrontSize(const MCSubtargetInfo *STI) { … }

unsigned getLocalMemorySize(const MCSubtargetInfo *STI) { … }

unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI) { … }

unsigned getEUsPerCU(const MCSubtargetInfo *STI) { … }

unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
                               unsigned FlatWorkGroupSize) { … }

unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) { … }

unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) { … }

unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
                                   unsigned FlatWorkGroupSize) { … }

unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) { … }

unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) { … }

unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
                              unsigned FlatWorkGroupSize) { … }

unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) { … }

unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI) { … }

unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) { … }

unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI) { … }

unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) { … }

unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
                        bool Addressable) { … }

unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
                          bool FlatScrUsed, bool XNACKUsed) { … }

unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
                          bool FlatScrUsed) { … }

static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs,
                                               unsigned Granule) { … }

unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) { … }

unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
                             std::optional<bool> EnableWavefrontSize32) { … }

unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
                                std::optional<bool> EnableWavefrontSize32) { … }

unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) { … }

unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) { … }

unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI) { … }

unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,
                                      unsigned NumVGPRs) { … }

unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
                                      unsigned MaxWaves,
                                      unsigned TotalNumVGPRs) { … }

unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
                                  AMDGPUSubtarget::Generation Gen) { … }

unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) { … }

unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) { … }

unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
                                 std::optional<bool> EnableWavefrontSize32) { … }

unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI,
                                   unsigned NumVGPRs,
                                   std::optional<bool> EnableWavefrontSize32) { … }
} // end namespace IsaInfo

void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &KernelCode,
                               const MCSubtargetInfo *STI) { … }

bool isGroupSegment(const GlobalValue *GV) { … }

bool isGlobalSegment(const GlobalValue *GV) { … }

bool isReadOnlySegment(const GlobalValue *GV) { … }

bool shouldEmitConstantsToTextSection(const Triple &TT) { … }

std::pair<unsigned, unsigned>
getIntegerPairAttribute(const Function &F, StringRef Name,
                        std::pair<unsigned, unsigned> Default,
                        bool OnlyFirstRequired) { … }

SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,
                                             unsigned Size) { … }

unsigned getVmcntBitMask(const IsaVersion &Version) { … }

unsigned getLoadcntBitMask(const IsaVersion &Version) { … }

unsigned getSamplecntBitMask(const IsaVersion &Version) { … }

unsigned getBvhcntBitMask(const IsaVersion &Version) { … }

unsigned getExpcntBitMask(const IsaVersion &Version) { … }

unsigned getLgkmcntBitMask(const IsaVersion &Version) { … }

unsigned getDscntBitMask(const IsaVersion &Version) { … }

unsigned getKmcntBitMask(const IsaVersion &Version) { … }

unsigned getStorecntBitMask(const IsaVersion &Version) { … }

unsigned getWaitcntBitMask(const IsaVersion &Version) { … }

unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) { … }

unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) { … }

unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) { … }

void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
                   unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) { … }

Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) { … }

unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
                     unsigned Vmcnt) { … }

unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
                      unsigned Expcnt) { … }

unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
                       unsigned Lgkmcnt) { … }

unsigned encodeWaitcnt(const IsaVersion &Version,
                       unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) { … }

unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) { … }

static unsigned getCombinedCountBitMask(const IsaVersion &Version,
                                        bool IsStore) { … }

Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt) { … }

Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt) { … }

static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt,
                              unsigned Loadcnt) { … }

static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt,
                               unsigned Storecnt) { … }

static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt,
                            unsigned Dscnt) { … }

static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt,
                                   unsigned Dscnt) { … }

unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded) { … }

static unsigned encodeStorecntDscnt(const IsaVersion &Version,
                                    unsigned Storecnt, unsigned Dscnt) { … }

unsigned encodeStorecntDscnt(const IsaVersion &Version,
                             const Waitcnt &Decoded) { … }

//===----------------------------------------------------------------------===//
// Custom Operand Values
//===----------------------------------------------------------------------===//

static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr,
                                                int Size,
                                                const MCSubtargetInfo &STI) { … }

static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr,
                                            int Size, unsigned Code,
                                            bool &HasNonDefaultVal,
                                            const MCSubtargetInfo &STI) { … }

static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size,
                                unsigned Code, int &Idx, StringRef &Name,
                                unsigned &Val, bool &IsDefault,
                                const MCSubtargetInfo &STI) { … }

static int encodeCustomOperandVal(const CustomOperandVal &Op,
                                  int64_t InputVal) { … }

static int encodeCustomOperand(const CustomOperandVal *Opr, int Size,
                               const StringRef Name, int64_t InputVal,
                               unsigned &UsedOprMask,
                               const MCSubtargetInfo &STI) { … }

//===----------------------------------------------------------------------===//
// DepCtr
//===----------------------------------------------------------------------===//

namespace DepCtr {

int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI) { … }

bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
                              const MCSubtargetInfo &STI) { … }

bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
                  bool &IsDefault, const MCSubtargetInfo &STI) { … }

int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
                 const MCSubtargetInfo &STI) { … }

unsigned decodeFieldVmVsrc(unsigned Encoded) { … }

unsigned decodeFieldVaVdst(unsigned Encoded) { … }

unsigned decodeFieldSaSdst(unsigned Encoded) { … }

unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc) { … }

unsigned encodeFieldVmVsrc(unsigned VmVsrc) { … }

unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst) { … }

unsigned encodeFieldVaVdst(unsigned VaVdst) { … }

unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst) { … }

unsigned encodeFieldSaSdst(unsigned SaSdst) { … }

} // namespace DepCtr

//===----------------------------------------------------------------------===//
// exp tgt
//===----------------------------------------------------------------------===//

namespace Exp {

struct ExpTgt { … };

static constexpr ExpTgt ExpTgtInfo[] = …;

bool getTgtName(unsigned Id, StringRef &Name, int &Index) { … }

unsigned getTgtId(const StringRef Name) { … }

bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) { … }

} // namespace Exp

//===----------------------------------------------------------------------===//
// MTBUF Format
//===----------------------------------------------------------------------===//

namespace MTBUFFormat {

int64_t getDfmt(const StringRef Name) { … }

StringRef getDfmtName(unsigned Id) { … }

static StringLiteral const *getNfmtLookupTable(const MCSubtargetInfo &STI) { … }

int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) { … }

StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) { … }

bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) { … }

bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) { … }

int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt) { … }

void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt) { … }

int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI) { … }

StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI) { … }

bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI) { … }

int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
                             const MCSubtargetInfo &STI) { … }

bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) { … }

unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI) { … }

} // namespace MTBUFFormat

//===----------------------------------------------------------------------===//
// SendMsg
//===----------------------------------------------------------------------===//

namespace SendMsg {

static uint64_t getMsgIdMask(const MCSubtargetInfo &STI) { … }

bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI) { … }

bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
                  bool Strict) { … }

bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
                      const MCSubtargetInfo &STI, bool Strict) { … }

bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) { … }

bool msgSupportsStream(int64_t MsgId, int64_t OpId,
                       const MCSubtargetInfo &STI) { … }

void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
               uint16_t &StreamId, const MCSubtargetInfo &STI) { … }

uint64_t encodeMsg(uint64_t MsgId,
                   uint64_t OpId,
                   uint64_t StreamId) { … }

} // namespace SendMsg

//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//

unsigned getInitialPSInputAddr(const Function &F) { … }

bool getHasColorExport(const Function &F) { … }

bool getHasDepthExport(const Function &F) { … }

bool isShader(CallingConv::ID cc) { … }

bool isGraphics(CallingConv::ID cc) { … }

bool isCompute(CallingConv::ID cc) { … }

bool isEntryFunctionCC(CallingConv::ID CC) { … }

bool isModuleEntryFunctionCC(CallingConv::ID CC) { … }

bool isChainCC(CallingConv::ID CC) { … }

bool isKernelCC(const Function *Func) { … }

bool hasXNACK(const MCSubtargetInfo &STI) { … }

bool hasSRAMECC(const MCSubtargetInfo &STI) { … }

bool hasMIMG_R128(const MCSubtargetInfo &STI) { … }

bool hasA16(const MCSubtargetInfo &STI) { … }

bool hasG16(const MCSubtargetInfo &STI) { … }

bool hasPackedD16(const MCSubtargetInfo &STI) { … }

bool hasGDS(const MCSubtargetInfo &STI) { … }

unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler) { … }

unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI) { … }

bool isSI(const MCSubtargetInfo &STI) { … }

bool isCI(const MCSubtargetInfo &STI) { … }

bool isVI(const MCSubtargetInfo &STI) { … }

bool isGFX9(const MCSubtargetInfo &STI) { … }

bool isGFX9_GFX10(const MCSubtargetInfo &STI) { … }

bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI) { … }

bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI) { … }

bool isGFX8Plus(const MCSubtargetInfo &STI) { … }

bool isGFX9Plus(const MCSubtargetInfo &STI) { … }

bool isNotGFX9Plus(const MCSubtargetInfo &STI) { … }

bool isGFX10(const MCSubtargetInfo &STI) { … }

bool isGFX10_GFX11(const MCSubtargetInfo &STI) { … }

bool isGFX10Plus(const MCSubtargetInfo &STI) { … }

bool isGFX11(const MCSubtargetInfo &STI) { … }

bool isGFX11Plus(const MCSubtargetInfo &STI) { … }

bool isGFX12(const MCSubtargetInfo &STI) { … }

bool isGFX12Plus(const MCSubtargetInfo &STI) { … }

bool isNotGFX12Plus(const MCSubtargetInfo &STI) { … }

bool isNotGFX11Plus(const MCSubtargetInfo &STI) { … }

bool isNotGFX10Plus(const MCSubtargetInfo &STI) { … }

bool isGFX10Before1030(const MCSubtargetInfo &STI) { … }

bool isGCN3Encoding(const MCSubtargetInfo &STI) { … }

bool isGFX10_AEncoding(const MCSubtargetInfo &STI) { … }

bool isGFX10_BEncoding(const MCSubtargetInfo &STI) { … }

bool hasGFX10_3Insts(const MCSubtargetInfo &STI) { … }

bool isGFX10_3_GFX11(const MCSubtargetInfo &STI) { … }

bool isGFX90A(const MCSubtargetInfo &STI) { … }

bool isGFX940(const MCSubtargetInfo &STI) { … }

bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) { … }

bool hasMAIInsts(const MCSubtargetInfo &STI) { … }

bool hasVOPD(const MCSubtargetInfo &STI) { … }

bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI) { … }

unsigned hasKernargPreload(const MCSubtargetInfo &STI) { … }

int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
                         int32_t ArgNumVGPR) { … }

bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI) { … }

bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI) { … }

#define MAP_REG2REG …

#define CASE_CI_VI …

#define CASE_VI_GFX9PLUS …

#define CASE_GFXPRE11_GFX11PLUS …

#define CASE_GFXPRE11_GFX11PLUS_TO …

MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI) { … }

#undef CASE_CI_VI
#undef CASE_VI_GFX9PLUS
#undef CASE_GFXPRE11_GFX11PLUS
#undef CASE_GFXPRE11_GFX11PLUS_TO

#define CASE_CI_VI …
#define CASE_VI_GFX9PLUS …
#define CASE_GFXPRE11_GFX11PLUS …
#define CASE_GFXPRE11_GFX11PLUS_TO …

MCRegister mc2PseudoReg(MCRegister Reg) { … }

bool isInlineValue(unsigned Reg) { … }

#undef CASE_CI_VI
#undef CASE_VI_GFX9PLUS
#undef CASE_GFXPRE11_GFX11PLUS
#undef CASE_GFXPRE11_GFX11PLUS_TO
#undef MAP_REG2REG

bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) { … }

bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo) { … }

bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) { … }

bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) { … }

// Avoid using MCRegisterClass::getSize, since that function will go away
// (move from MC* level to Target* level). Return size in bits.
unsigned getRegBitWidth(unsigned RCID) { … }

unsigned getRegBitWidth(const MCRegisterClass &RC) { … }

unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
                           unsigned OpNo) { … }

bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) { … }

bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) { … }

bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi) { … }

bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi) { … }

bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi) { … }

std::optional<unsigned> getInlineEncodingV216(bool IsFloat, uint32_t Literal) { … }

// Encoding of the literal as an inline constant for a V_PK_*_IU16 instruction
// or nullopt.
std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal) { … }

// Encoding of the literal as an inline constant for a V_PK_*_BF16 instruction
// or nullopt.
std::optional<unsigned> getInlineEncodingV2BF16(uint32_t Literal) { … }

// Encoding of the literal as an inline constant for a V_PK_*_F16 instruction
// or nullopt.
std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal) { … }

// Whether the given literal can be inlined for a V_PK_* instruction.
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType) { … }

// Whether the given literal can be inlined for a V_PK_*_IU16 instruction.
bool isInlinableLiteralV2I16(uint32_t Literal) { … }

// Whether the given literal can be inlined for a V_PK_*_BF16 instruction.
bool isInlinableLiteralV2BF16(uint32_t Literal) { … }

// Whether the given literal can be inlined for a V_PK_*_F16 instruction.
bool isInlinableLiteralV2F16(uint32_t Literal) { … }

bool isValid32BitLiteral(uint64_t Val, bool IsFP64) { … }

bool isArgPassedInSGPR(const Argument *A) { … }

bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo) { … }

static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) { … }

bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
                                      int64_t EncodedOffset) { … }

bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
                                    int64_t EncodedOffset,
                                    bool IsBuffer) { … }

static bool isDwordAligned(uint64_t ByteOffset) { … }

uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST,
                                uint64_t ByteOffset) { … }

std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
                                            int64_t ByteOffset, bool IsBuffer,
                                            bool HasSOffset) { … }

std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
                                                     int64_t ByteOffset) { … }

unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST) { … }

namespace {

struct SourceOfDivergence { … };
const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);

struct AlwaysUniform { … };
const AlwaysUniform *lookupAlwaysUniform(unsigned Intr);

#define GET_SourcesOfDivergence_IMPL
#define GET_UniformIntrinsics_IMPL
#define GET_Gfx9BufferFormat_IMPL
#define GET_Gfx10BufferFormat_IMPL
#define GET_Gfx11PlusBufferFormat_IMPL
#include "AMDGPUGenSearchableTables.inc"

} // end anonymous namespace

bool isIntrinsicSourceOfDivergence(unsigned IntrID) { … }

bool isIntrinsicAlwaysUniform(unsigned IntrID) { … }

const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
                                                  uint8_t NumComponents,
                                                  uint8_t NumFormat,
                                                  const MCSubtargetInfo &STI) { … }

const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
                                                  const MCSubtargetInfo &STI) { … }

bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) { … }

bool isDPALU_DPP(const MCInstrDesc &OpDesc) { … }

unsigned getLdsDwGranularity(const MCSubtargetInfo &ST) { … }

} // namespace AMDGPU

raw_ostream &operator<<(raw_ostream &OS,
                        const AMDGPU::IsaInfo::TargetIDSetting S) { … }

} // namespace llvm
llvm/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
