//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "AMDKernelCodeT.h" #include "MCTargetDesc/AMDGPUInstPrinter.h" #include "MCTargetDesc/AMDGPUMCExpr.h" #include "MCTargetDesc/AMDGPUMCKernelDescriptor.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUTargetStreamer.h" #include "SIDefines.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" #include "TargetInfo/AMDGPUTargetInfo.h" #include "Utils/AMDGPUAsmUtils.h" #include "Utils/AMDGPUBaseInfo.h" #include "Utils/AMDKernelCodeTUtils.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/StringSet.h" #include "llvm/ADT/Twine.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/CodeGenTypes/MachineValueType.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/AMDGPUMetadata.h" #include "llvm/Support/AMDHSAKernelDescriptor.h" #include "llvm/Support/Casting.h" #include "llvm/Support/MathExtras.h" #include "llvm/TargetParser/TargetParser.h" #include <optional> usingnamespacellvm; usingnamespacellvm::AMDGPU; usingnamespacellvm::amdhsa; namespace { class AMDGPUAsmParser; enum RegisterKind { … }; //===----------------------------------------------------------------------===// // Operand //===----------------------------------------------------------------------===// class AMDGPUOperand : public MCParsedAsmOperand { … }; raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) { … } //===----------------------------------------------------------------------===// // AsmParser //===----------------------------------------------------------------------===// // Holds info related to the current kernel, e.g. count of SGPRs used. // Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next // .amdgpu_hsa_kernel or at EOF. class KernelScopeInfo { … }; class AMDGPUAsmParser : public MCTargetAsmParser { … }; } // end anonymous namespace // May be called with integer type with equivalent bitwidth. static const fltSemantics *getFltSemantics(unsigned Size) { … } static const fltSemantics *getFltSemantics(MVT VT) { … } static const fltSemantics *getOpFltSemantics(uint8_t OperandType) { … } //===----------------------------------------------------------------------===// // Operand //===----------------------------------------------------------------------===// static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) { … } static bool isSafeTruncation(int64_t Val, unsigned Size) { … } static bool isInlineableLiteralOp16(int64_t Val, MVT VT, bool HasInv2Pi) { … } bool AMDGPUOperand::isInlinableImm(MVT type) const { … } bool AMDGPUOperand::isLiteralImm(MVT type) const { … } bool AMDGPUOperand::isRegClass(unsigned RCID) const { … } bool AMDGPUOperand::isVRegWithInputMods() const { … } template <bool IsFake16> bool AMDGPUOperand::isT16_Lo128VRegWithInputMods() const { … } template <bool IsFake16> bool AMDGPUOperand::isT16VRegWithInputMods() const { … } bool AMDGPUOperand::isSDWAOperand(MVT type) const { … } bool AMDGPUOperand::isSDWAFP16Operand() const { … } bool AMDGPUOperand::isSDWAFP32Operand() const { … } bool AMDGPUOperand::isSDWAInt16Operand() const { … } bool AMDGPUOperand::isSDWAInt32Operand() const { … } bool AMDGPUOperand::isBoolReg() const { … } uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const { … } void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const { … } void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const { … } void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const { … } bool AMDGPUOperand::isInlineValue() const { … } //===----------------------------------------------------------------------===// // AsmParser //===----------------------------------------------------------------------===// void AMDGPUAsmParser::createConstantSymbol(StringRef Id, int64_t Val) { … } static int getRegClass(RegisterKind Is, unsigned RegWidth) { … } static MCRegister getSpecialRegForName(StringRef RegName) { … } bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, bool RestoreOnFailure) { … } bool AMDGPUAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } ParseStatus AMDGPUAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } bool AMDGPUAsmParser::AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth, RegisterKind RegKind, MCRegister Reg1, SMLoc Loc) { … } struct RegInfo { … }; static constexpr RegInfo RegularRegisters[] = …; static bool isRegularReg(RegisterKind Kind) { … } static const RegInfo* getRegularRegInfo(StringRef Str) { … } static bool getRegNum(StringRef Str, unsigned& Num) { … } bool AMDGPUAsmParser::isRegister(const AsmToken &Token, const AsmToken &NextToken) const { … } bool AMDGPUAsmParser::isRegister() { … } MCRegister AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum, unsigned SubReg, unsigned RegWidth, SMLoc Loc) { … } bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) { … } MCRegister AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) { … } MCRegister AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) { … } MCRegister AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) { … } bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, MCRegister &Reg, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) { … } bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, MCRegister &Reg, unsigned &RegNum, unsigned &RegWidth, bool RestoreOnFailure /*=false*/) { … } std::optional<StringRef> AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) { … } void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) { … } bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { … } std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) { … } ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands, bool HasSP3AbsModifier, bool HasLit) { … } ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod, bool HasLit) { … } bool AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const { … } bool AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const { … } bool AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const { … } bool AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const { … } // Check if this is an operand modifier or an opcode modifier // which may look like an expression but it is not. We should // avoid parsing these modifiers as expressions. Currently // recognized sequences are: // |...| // abs(...) // neg(...) // sext(...) // -reg // -|...| // -abs(...) // name:... // bool AMDGPUAsmParser::isModifier() { … } // Check if the current token is an SP3 'neg' modifier. // Currently this modifier is allowed in the following context: // // 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]". // 2. Before an 'abs' modifier: -abs(...) // 3. Before an SP3 'abs' modifier: -|...| // // In all other cases "-" is handled as a part // of an expression that follows the sign. // // Note: When "-" is followed by an integer literal, // this is interpreted as integer negation rather // than a floating-point NEG modifier applied to N. // Beside being contr-intuitive, such use of floating-point // NEG modifier would have resulted in different meaning // of integer literals used with VOP1/2/C and VOP3, // for example: // v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF // v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001 // Negative fp literals with preceding "-" are // handled likewise for uniformity // bool AMDGPUAsmParser::parseSP3NegModifier() { … } ParseStatus AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands, bool AllowImm) { … } ParseStatus AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands, bool AllowImm) { … } ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) { … } unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) { … } static ArrayRef<unsigned> getAllVariants() { … } // What asm variants we should check ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const { … } StringRef AMDGPUAsmParser::getMatchedVariantName() const { … } unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const { … } // NB: This code is correct only when used to check constant // bus limitations because GFX7 support no f16 inline constants. // Note that there are no cases when a GFX7 opcode violates // constant bus limitations due to the use of an f16 constant. bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst, unsigned OpIdx) const { … } unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const { … } constexpr unsigned MAX_SRC_OPERANDS_NUM = …; OperandIndices; // Get regular operand indices in the same order as specified // in the instruction (but append mandatory literals to the end). static OperandIndices getSrcOperandIndices(unsigned Opcode, bool AddMandatoryLiterals = false) { … } bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) { … } // Based on the comment for `AMDGPUInstructionSelector::selectWritelane`: // Writelane is special in that it can use SGPR and M0 (which would normally // count as using the constant bus twice - but in this case it is allowed since // the lane selector doesn't count as a use of the constant bus). However, it is // still required to abide by the 1 SGPR rule. static bool checkWriteLane(const MCInst &Inst) { … } bool AMDGPUAsmParser::validateConstantBusLimitations( const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateVOPDRegBankConstraints( const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) { … } constexpr uint64_t MIMGFlags = …; bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc) { … } bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc) { … } bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) { … } bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) { … } bool AMDGPUAsmParser::validateMIMGDim(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) { … } static bool IsMovrelsSDWAOpcode(const unsigned Opcode) { … } // movrels* opcodes should only allow VGPRS as src0. // This is specified in .td description for vop1/vop3, // but sdwa is handled differently. See isSDWAOperand. bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) { … } bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) { … } static bool IsRevOpcode(const unsigned Opcode) { … } std::optional<StringRef> AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) { … } SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const { … } bool AMDGPUAsmParser::validateOffset(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst, const OperandVector &Operands) { … } SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const { … } bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const { … } bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) { … } bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) { … } bool AMDGPUAsmParser::validateDPP(const MCInst &Inst, const OperandVector &Operands) { … } // Check if VCC register matches wavefront size bool AMDGPUAsmParser::validateVccOperand(MCRegister Reg) const { … } // One unique literal can be used. VOP3 literal is only allowed in GFX10+ bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands) { … } // Returns -1 if not a register, 0 if VGPR and 1 if AGPR. static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, const MCRegisterInfo *MRI) { … } bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const { … } bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const { … } SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const { … } bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateDS(const MCInst &Inst, const OperandVector &Operands) { … } // gfx90a has an undocumented limitation: // DS_GWS opcodes must use even aligned registers. bool AMDGPUAsmParser::validateGWS(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands, const SMLoc &IDLoc) { … } bool AMDGPUAsmParser::validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands, const unsigned CPol) { … } bool AMDGPUAsmParser::validateTFE(const MCInst &Inst, const OperandVector &Operands) { … } bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands) { … } static std::string AMDGPUMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID = 0); static bool AMDGPUCheckMnemonic(StringRef Mnemonic, const FeatureBitset &AvailableFeatures, unsigned VariantID); bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo, const FeatureBitset &FBS) { … } bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo, const FeatureBitset &FBS, ArrayRef<unsigned> Variants) { … } bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo, const SMLoc &IDLoc) { … } static bool isInvalidVOPDY(const OperandVector &Operands, uint64_t InvalidOprIdx) { … } bool AMDGPUAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { … } bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) { … } bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() { … } bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) { … } bool AMDGPUAsmParser::calculateGPRBlocks( const FeatureBitset &Features, const MCExpr *VCCUsed, const MCExpr *FlatScrUsed, bool XNACKUsed, std::optional<bool> EnableWavefrontSize32, const MCExpr *NextFreeVGPR, SMRange VGPRRange, const MCExpr *NextFreeSGPR, SMRange SGPRRange, const MCExpr *&VGPRBlocks, const MCExpr *&SGPRBlocks) { … } bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { … } bool AMDGPUAsmParser::ParseDirectiveAMDHSACodeObjectVersion() { … } bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID, AMDGPUMCKernelCodeT &C) { … } bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() { … } bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() { … } bool AMDGPUAsmParser::ParseDirectiveISAVersion() { … } bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() { … } /// Common code to parse out a block of text (typically YAML) between start and /// end directives. bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin, const char *AssemblerDirectiveEnd, std::string &CollectString) { … } /// Parse the assembler directive for new MsgPack-format PAL metadata. bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() { … } /// Parse the assembler directive for old linear-format PAL metadata. bool AMDGPUAsmParser::ParseDirectivePALMetadata() { … } /// ParseDirectiveAMDGPULDS /// ::= .amdgpu_lds identifier ',' size_expression [',' align_expression] bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() { … } bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { … } bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI, MCRegister Reg) { … } ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, OperandMode Mode) { … } StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) { … } static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID); bool AMDGPUAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // Utility functions //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name, OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &IntVal) { … } ParseStatus AMDGPUAsmParser::parseIntWithPrefix( const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy, std::function<bool(int64_t &)> ConvertResult) { … } ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix( const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy, bool (*ConvertResult)(int64_t &)) { … } ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy) { … } unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo, bool &Disabling) const { … } ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseScope(OperandVector &Operands, int64_t &Scope) { … } ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) { … } static void addOptionalImmOperand( MCInst& Inst, const OperandVector& Operands, AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx, AMDGPUOperand::ImmTy ImmT, int64_t Default = 0) { … } ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value, SMLoc &StringLoc) { … } ParseStatus AMDGPUAsmParser::parseStringOrIntWithPrefix( OperandVector &Operands, StringRef Name, ArrayRef<const char *> Ids, int64_t &IntVal) { … } ParseStatus AMDGPUAsmParser::parseStringOrIntWithPrefix( OperandVector &Operands, StringRef Name, ArrayRef<const char *> Ids, AMDGPUOperand::ImmTy Type) { … } //===----------------------------------------------------------------------===// // MTBUF format //===----------------------------------------------------------------------===// bool AMDGPUAsmParser::tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Fmt) { … } ParseStatus AMDGPUAsmParser::tryParseIndexKey(OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy) { … } ParseStatus AMDGPUAsmParser::parseIndexKey8bit(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseIndexKey16bit(OperandVector &Operands) { … } // dfmt and nfmt (in a tbuffer instruction) are parsed as one to allow their // values to live in a joint format operand in the MCInst encoding. ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) { … } ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) { … } bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc) { … } ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr, SMLoc FormatLoc, int64_t &Format) { … } ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr, SMLoc Loc, int64_t &Format) { … } ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) { … } ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) { … } ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // Exp //===----------------------------------------------------------------------===// void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // s_waitcnt //===----------------------------------------------------------------------===// static bool encodeCnt( const AMDGPU::IsaVersion ISA, int64_t &IntVal, int64_t CntVal, bool Saturate, unsigned (*encode)(const IsaVersion &Version, unsigned, unsigned), unsigned (*decode)(const IsaVersion &Version, unsigned)) { … } bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) { … } ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) { … } bool AMDGPUAsmParser::parseDelay(int64_t &Delay) { … } ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) { … } bool AMDGPUOperand::isSWaitCnt() const { … } bool AMDGPUOperand::isSDelayALU() const { … } //===----------------------------------------------------------------------===// // DepCtr //===----------------------------------------------------------------------===// void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName) { … } bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) { … } ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) { … } bool AMDGPUOperand::isDepCtr() const { … } //===----------------------------------------------------------------------===// // hwreg //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseHwregFunc(OperandInfoTy &HwReg, OperandInfoTy &Offset, OperandInfoTy &Width) { … } ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) { … } bool AMDGPUOperand::isHwreg() const { … } //===----------------------------------------------------------------------===// // sendmsg //===----------------------------------------------------------------------===// bool AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream) { … } bool AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg, const OperandInfoTy &Op, const OperandInfoTy &Stream) { … } ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) { … } bool AMDGPUOperand::isSendMsg() const { … } //===----------------------------------------------------------------------===// // v_interp //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) { … } ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // exp //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // parser helpers //===----------------------------------------------------------------------===// bool AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const { … } bool AMDGPUAsmParser::isId(const StringRef Id) const { … } bool AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const { … } StringRef AMDGPUAsmParser::getId() const { … } bool AMDGPUAsmParser::trySkipId(const StringRef Id) { … } bool AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) { … } bool AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) { … } bool AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) { … } bool AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg) { … } bool AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) { … } bool AMDGPUAsmParser::parseExpr(OperandVector &Operands) { … } bool AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) { … } bool AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) { … } AsmToken AMDGPUAsmParser::getToken() const { … } AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) { … } void AMDGPUAsmParser::peekTokens(MutableArrayRef<AsmToken> Tokens) { … } AsmToken::TokenKind AMDGPUAsmParser::getTokenKind() const { … } SMLoc AMDGPUAsmParser::getLoc() const { … } StringRef AMDGPUAsmParser::getTokenStr() const { … } void AMDGPUAsmParser::lex() { … } SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const { … } SMLoc AMDGPUAsmParser::getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test, const OperandVector &Operands) const { … } SMLoc AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const { … } SMLoc AMDGPUAsmParser::getRegLoc(MCRegister Reg, const OperandVector &Operands) const { … } SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands, bool SearchMandatoryLiterals) const { … } SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const { … } SMLoc AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const { … } ParseStatus AMDGPUAsmParser::parseStructuredOpFields(ArrayRef<StructuredOpField *> Fields) { … } bool AMDGPUAsmParser::validateStructuredOpFields( ArrayRef<const StructuredOpField *> Fields) { … } //===----------------------------------------------------------------------===// // swizzle //===----------------------------------------------------------------------===// LLVM_READNONE static unsigned encodeBitmaskPerm(const unsigned AndMask, const unsigned OrMask, const unsigned XorMask) { … } bool AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op, const unsigned MinVal, const unsigned MaxVal, const Twine &ErrMsg, SMLoc &Loc) { … } bool AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op, const unsigned MinVal, const unsigned MaxVal, const StringRef ErrMsg) { … } bool AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleRotate(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) { … } bool AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) { … } ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) { … } bool AMDGPUOperand::isSwizzle() const { … } //===----------------------------------------------------------------------===// // VGPR Index Mode //===----------------------------------------------------------------------===// int64_t AMDGPUAsmParser::parseGPRIdxMacro() { … } ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) { … } bool AMDGPUOperand::isGPRIdxMode() const { … } //===----------------------------------------------------------------------===// // sopp branch targets //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // Boolean holding registers //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // mubuf //===----------------------------------------------------------------------===// void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst, const OperandVector &Operands, bool IsAtomic) { … } //===----------------------------------------------------------------------===// // smrd //===----------------------------------------------------------------------===// bool AMDGPUOperand::isSMRDOffset8() const { … } bool AMDGPUOperand::isSMEMOffset() const { … } bool AMDGPUOperand::isSMRDLiteralOffset() const { … } //===----------------------------------------------------------------------===// // vop3 //===----------------------------------------------------------------------===// static bool ConvertOmodMul(int64_t &Mul) { … } static bool ConvertOmodDiv(int64_t &Div) { … } // For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1. // This is intentional and ensures compatibility with sp3. // See bug 35397 for details. bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) { … } void AMDGPUAsmParser::onBeginOfFile() { … } /// Parse AMDGPU specific expressions. /// /// expr ::= or(expr, ...) | /// max(expr, ...) /// bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) { … } ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) { … } // Determines which bit DST_OP_SEL occupies in the op_sel operand according to // the number of src operands present, then copies that bit into src0_modifiers. static void cvtVOP3DstOpSelOnly(MCInst &Inst, const MCRegisterInfo &MRI) { … } void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands, OptionalImmIndexMap &OptionalIdx) { … } static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) { … } void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands, OptionalImmIndexMap &OptionalIdx) { … } void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands, OptionalImmIndexMap &OptIdx) { … } void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) { … } static void addSrcModifiersAndSrc(MCInst &Inst, const OperandVector &Operands, unsigned i, unsigned Opc, unsigned OpName) { … } void AMDGPUAsmParser::cvtSWMMAC(MCInst &Inst, const OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // VOPD //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) { … } // Create VOPD MCInst operands using parsed assembler operands. void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // dpp //===----------------------------------------------------------------------===// bool AMDGPUOperand::isDPP8() const { … } bool AMDGPUOperand::isDPPCtrl() const { … } //===----------------------------------------------------------------------===// // mAI //===----------------------------------------------------------------------===// bool AMDGPUOperand::isBLGP() const { … } bool AMDGPUOperand::isS16Imm() const { … } bool AMDGPUOperand::isU16Imm() const { … } //===----------------------------------------------------------------------===// // dim //===----------------------------------------------------------------------===// bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) { … } ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) { … } //===----------------------------------------------------------------------===// // dpp //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) { … } bool AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands) { … } int64_t AMDGPUAsmParser::parseDPPCtrlPerm() { … } int64_t AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) { … } ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { … } void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) { … } void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) { … } //===----------------------------------------------------------------------===// // sdwa //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix, AMDGPUOperand::ImmTy Type) { … } ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { … } void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) { … } void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands, uint64_t BasicInstType, bool SkipDstVcc, bool SkipSrcVcc) { … } /// Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() { … } #define GET_REGISTER_MATCHER #define GET_MATCHER_IMPLEMENTATION #define GET_MNEMONIC_SPELL_CHECKER #define GET_MNEMONIC_CHECKER #include "AMDGPUGenAsmMatcher.inc" ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) { … } // This function should be defined after auto-generated include so that we have // MatchClassKind enum defined unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) { … } //===----------------------------------------------------------------------===// // endpgm //===----------------------------------------------------------------------===// ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) { … } bool AMDGPUOperand::isEndpgm() const { … } //===----------------------------------------------------------------------===// // Split Barrier //===----------------------------------------------------------------------===// bool AMDGPUOperand::isSplitBarrier() const { … }
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