//===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines the hazard recognizer for scheduling on Hexagon. // Use a DFA based hazard recognizer. // //===----------------------------------------------------------------------===// #include "HexagonHazardRecognizer.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include <cassert> usingnamespacellvm; #define DEBUG_TYPE … void HexagonHazardRecognizer::Reset() { … } ScheduleHazardRecognizer::HazardType HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { … } void HexagonHazardRecognizer::AdvanceCycle() { … } /// Handle the cases when we prefer one instruction over another. Case 1 - we /// prefer not to generate multiple loads in the packet to avoid a potential /// bank conflict. Case 2 - if a packet contains a dot cur instruction, then we /// prefer the instruction that can use the dot cur result. However, if the use /// is not scheduled in the same packet, then prefer other instructions in the /// subsequent packet. Case 3 - we prefer a vector store that can be converted /// to a .new store. The packetizer will not generate the .new store if the /// store doesn't have resources to fit in the packet (but the .new store may /// have resources). We attempt to schedule the store as soon as possible to /// help packetize the two instructions together. bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) { … } /// Return true if the instruction would be converted to a new value store when /// packetized. bool HexagonHazardRecognizer::isNewStore(MachineInstr &MI) { … } void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { … }