HexagonISelDAGToDAG.cpp | Explore in Territory

//===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the Hexagon target.
//
//===----------------------------------------------------------------------===//

#include "HexagonISelDAGToDAG.h"
#include "Hexagon.h"
#include "HexagonISelLowering.h"
#include "HexagonMachineFunctionInfo.h"
#include "HexagonTargetMachine.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsHexagon.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
usingnamespacellvm;

#define DEBUG_TYPE …
#define PASS_NAME …

static
cl::opt<bool>
EnableAddressRebalancing("isel-rebalance-addr", cl::Hidden, cl::init(true),
  cl::desc("Rebalance address calculation trees to improve "
          "instruction selection"));

// Rebalance only if this allows e.g. combining a GA with an offset or
// factoring out a shift.
static
cl::opt<bool>
RebalanceOnlyForOptimizations("rebalance-only-opt", cl::Hidden, cl::init(false),
  cl::desc("Rebalance address tree only if this allows optimizations"));

static
cl::opt<bool>
RebalanceOnlyImbalancedTrees("rebalance-only-imbal", cl::Hidden,
  cl::init(false), cl::desc("Rebalance address tree only if it is imbalanced"));

static cl::opt<bool> CheckSingleUse("hexagon-isel-su", cl::Hidden,
  cl::init(true), cl::desc("Enable checking of SDNode's single-use status"));

//===----------------------------------------------------------------------===//
// Instruction Selector Implementation
//===----------------------------------------------------------------------===//

#define GET_DAGISEL_BODY …
#include "HexagonGenDAGISel.inc"

namespace llvm {
/// createHexagonISelDag - This pass converts a legalized DAG into a
/// Hexagon-specific DAG, ready for instruction scheduling.
FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
                                   CodeGenOptLevel OptLevel) { … }
}

HexagonDAGToDAGISelLegacy::HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm,
                                                     CodeGenOptLevel OptLevel)
    : … { … }

char HexagonDAGToDAGISelLegacy::ID = …;

INITIALIZE_PASS(…)

void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { … }

MachineSDNode *HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(SDNode *IntN) { … }

SDNode *HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(MachineSDNode *LoadN,
      SDNode *IntN) { … }

bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) { … }

// Convert the bit-reverse load intrinsic to appropriate target instruction.
bool HexagonDAGToDAGISel::SelectBrevLdIntrinsic(SDNode *IntN) { … }

/// Generate a machine instruction node for the new circular buffer intrinsics.
/// The new versions use a CSx register instead of the K field.
bool HexagonDAGToDAGISel::SelectNewCircIntrinsic(SDNode *IntN) { … }

void HexagonDAGToDAGISel::SelectLoad(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) { … }

void HexagonDAGToDAGISel::SelectStore(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectSHL(SDNode *N) { … }

//
// Handling intrinsics for circular load and bitreverse load.
//
void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectExtractSubvector(SDNode *N) { … }

//
// Map floating point constant values.
//
void HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) { … }

//
// Map boolean values.
//
void HexagonDAGToDAGISel::SelectConstant(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectAddSubCarry(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectVAlign(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectVAlignAddr(SDNode *N) { … }

// Handle these nodes here to avoid having to write patterns for all
// combinations of input/output types. In all cases, the resulting
// instruction is the same.
void HexagonDAGToDAGISel::SelectTypecast(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectP2D(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectD2P(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) { … }

void HexagonDAGToDAGISel::FDiv(SDNode *N) { … }

void HexagonDAGToDAGISel::FastFDiv(SDNode *N) { … }

void HexagonDAGToDAGISel::SelectFDiv(SDNode *N) { … }

void HexagonDAGToDAGISel::Select(SDNode *N) { … }

bool HexagonDAGToDAGISel::SelectInlineAsmMemoryOperand(
    const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
    std::vector<SDValue> &OutOps) { … }

static bool isMemOPCandidate(SDNode *I, SDNode *U) { … }


// Transform: (or (select c x 0) z)  ->  (select c (or x z) z)
//            (or (select c 0 y) z)  ->  (select c z (or y z))
void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) { … }

// Transform: (store ch val (add x (add (shl y c) e)))
//        to: (store ch val (add x (shl (add y d) c))),
// where e = (shl d c) for some integer d.
// The purpose of this is to enable generation of loads/stores with
// shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift
// value c must be 0, 1 or 2.
void HexagonDAGToDAGISel::ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes) { … }

// Transform: (load ch (add x (and (srl y c) Mask)))
//        to: (load ch (add x (shl (srl y d) d-c)))
// where
// Mask = 00..0 111..1 0.0
//          |     |     +-- d-c 0s, and d-c is 0, 1 or 2.
//          |     +-------- 1s
//          +-------------- at most c 0s
// Motivating example:
// DAG combiner optimizes (add x (shl (srl y 5) 2))
//                     to (add x (and (srl y 3) 1FFFFFFC))
// which results in a constant-extended and(##...,lsr). This transformation
// undoes this simplification for cases where the shl can be folded into
// an addressing mode.
void HexagonDAGToDAGISel::ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes) { … }

// Transform: (op ... (zext i1 c) ...) -> (select c (op ... 0 ...)
//                                                  (op ... 1 ...))
void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) { … }

void HexagonDAGToDAGISel::PreprocessISelDAG() { … }

void HexagonDAGToDAGISel::emitFunctionEntryCode() { … }

void HexagonDAGToDAGISel::updateAligna() { … }

// Match a frame index that can be used in an addressing mode.
bool HexagonDAGToDAGISel::SelectAddrFI(SDValue &N, SDValue &R) { … }

inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) { … }

inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) { … }

inline bool HexagonDAGToDAGISel::SelectAnyImm(SDValue &N, SDValue &R) { … }

inline bool HexagonDAGToDAGISel::SelectAnyImm0(SDValue &N, SDValue &R) { … }
inline bool HexagonDAGToDAGISel::SelectAnyImm1(SDValue &N, SDValue &R) { … }
inline bool HexagonDAGToDAGISel::SelectAnyImm2(SDValue &N, SDValue &R) { … }
inline bool HexagonDAGToDAGISel::SelectAnyImm3(SDValue &N, SDValue &R) { … }

inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) { … }

bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R,
                                             Align Alignment) { … }

bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
                                              bool UseGP, Align Alignment) { … }

bool HexagonDAGToDAGISel::DetectUseSxtw(SDValue &N, SDValue &R) { … }

bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits,
      SDValue &Src) { … }

bool HexagonDAGToDAGISel::isAlignedMemNode(const MemSDNode *N) const { … }

bool HexagonDAGToDAGISel::isSmallStackStore(const StoreSDNode *N) const { … }

// Return true when the given node fits in a positive half word.
bool HexagonDAGToDAGISel::isPositiveHalfWord(const SDNode *N) const { … }

bool HexagonDAGToDAGISel::hasOneUse(const SDNode *N) const { … }

////////////////////////////////////////////////////////////////////////////////
// Rebalancing of address calculation trees

static bool isOpcodeHandled(const SDNode *N) { … }

/// Return the weight of an SDNode
int HexagonDAGToDAGISel::getWeight(SDNode *N) { … }

int HexagonDAGToDAGISel::getHeight(SDNode *N) { … }

namespace {
struct WeightedLeaf { … };

/// A specialized priority queue for WeigthedLeaves. It automatically folds
/// constants and allows removal of non-top elements while maintaining the
/// priority order.
class LeafPrioQueue { … };
} // end anonymous namespace

WeightedLeaf LeafPrioQueue::findSHL(uint64_t MaxAmount) { … }

WeightedLeaf LeafPrioQueue::findMULbyConst() { … }

SDValue HexagonDAGToDAGISel::getMultiplierForSHL(SDNode *N) { … }

/// @returns the value x for which 2^x is a factor of Val
static unsigned getPowerOf2Factor(SDValue Val) { … }

/// @returns true if V>>Amount will eliminate V's operation on its child
static bool willShiftRightEliminate(SDValue V, unsigned Amount) { … }

SDValue HexagonDAGToDAGISel::factorOutPowerOf2(SDValue V, unsigned Power) { … }

static bool isTargetConstant(const SDValue &V) { … }

unsigned HexagonDAGToDAGISel::getUsesInFunction(const Value *V) { … }

/// Note - After calling this, N may be dead. It may have been replaced by a
/// new node, so always use the returned value in place of N.
///
/// @returns The SDValue taking the place of N (which could be N if it is
/// unchanged)
SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { … }

void HexagonDAGToDAGISel::rebalanceAddressTrees() { … }
llvm/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
