llvm/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp

//===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This implements the checking of insns inside a bundle according to the
// packet constraint rules of the Hexagon ISA.
//
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/HexagonMCChecker.h"
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCShuffler.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"

#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/SourceMgr.h"
#include <cassert>

usingnamespacellvm;

static cl::opt<bool>
    RelaxNVChecks("relax-nv-checks", cl::Hidden,
                  cl::desc("Relax checks of new-value validity"));

const HexagonMCChecker::PredSense
    HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);

void HexagonMCChecker::init() { … }

void HexagonMCChecker::initReg(MCInst const &MCI, MCRegister R,
                               MCRegister &PredReg, bool &isTrue) { … }

void HexagonMCChecker::init(MCInst const &MCI) { … }

HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
                                   MCSubtargetInfo const &STI, MCInst &mcb,
                                   MCRegisterInfo const &ri, bool ReportErrors)
    : … { … }

HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,
                                   MCSubtargetInfo const &STI,
                                   bool CopyReportErrors)
    : … { … }

bool HexagonMCChecker::check(bool FullCheck) { … }

static bool isDuplexAGroup(unsigned Opcode) { … }

static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) { … }

bool HexagonMCChecker::checkAXOK() { … }

void HexagonMCChecker::reportBranchErrors() { … }

bool HexagonMCChecker::checkHWLoop() { … }

bool HexagonMCChecker::checkCOFMax1() { … }

bool HexagonMCChecker::checkSlots() { … }

// Check legal use of predicate registers.
bool HexagonMCChecker::checkPredicates() { … }

// Check legal use of new values.
bool HexagonMCChecker::checkNewValues() { … }

bool HexagonMCChecker::checkRegistersReadOnly() { … }

bool HexagonMCChecker::registerUsed(MCRegister Register) { … }

std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
HexagonMCChecker::registerProducer(
    MCRegister Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) { … }

void HexagonMCChecker::checkRegisterCurDefs() { … }

// Check for legal register uses and definitions.
bool HexagonMCChecker::checkRegisters() { … }

// Check for legal use of solo insns.
bool HexagonMCChecker::checkSolo() { … }

bool HexagonMCChecker::checkShuffle() { … }

bool HexagonMCChecker::checkValidTmpDst() { … }

void HexagonMCChecker::compoundRegisterMap(unsigned &Register) { … }

void HexagonMCChecker::reportErrorRegisters(unsigned Register) { … }

void HexagonMCChecker::reportErrorNewValue(unsigned Register) { … }

void HexagonMCChecker::reportError(Twine const &Msg) { … }

void HexagonMCChecker::reportError(SMLoc Loc, Twine const &Msg) { … }

void HexagonMCChecker::reportNote(SMLoc Loc, llvm::Twine const &Msg) { … }

void HexagonMCChecker::reportWarning(Twine const &Msg) { … }

bool HexagonMCChecker::checkLegalVecRegPair() { … }

// Vd.tmp can't be accumulated
bool HexagonMCChecker::checkHVXAccum()
{ … }