HexagonMCCodeEmitter.cpp | Explore in Territory

//===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/HexagonMCCodeEmitter.h"
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "MCTargetDesc/HexagonFixupKinds.h"
#include "MCTargetDesc/HexagonMCExpr.h"
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/EndianStream.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
#include <map>
#include <string>
#include <vector>

#define DEBUG_TYPE …

usingnamespacellvm;
usingnamespaceHexagon;

STATISTIC(MCNumEmitted, "Number of MC instructions emitted");

static const unsigned fixup_Invalid = …;

#define _ …
#define P …
static const std::map<unsigned, std::vector<unsigned>> ExtFixups = …;
// [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned.

static const std::map<unsigned, std::vector<unsigned>> StdFixups = …;
//
// [2] The actual fixup is LO16 or HI16, depending on the instruction.
#undef P
#undef _

uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
                                         MCInst const &MCI) const { … }

/// Emit the bundle.
void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI,
                                             SmallVectorImpl<char> &CB,
                                             SmallVectorImpl<MCFixup> &Fixups,
                                             const MCSubtargetInfo &STI) const { … }

static bool RegisterMatches(MCRegister Consumer, MCRegister Producer,
                            MCRegister Producer2) { … }

void HexagonMCCodeEmitter::encodeSingleInstruction(
    const MCInst &MI, SmallVectorImpl<char> &CB,
    SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
    uint32_t Parse) const { … }

[[noreturn]] static void raise_relocation_error(unsigned Width, unsigned Kind) { … }

/// Some insns are not extended and thus have no bits. These cases require
/// a more brute force method for determining the correct relocation.
Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
      MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
      const MCSymbolRefExpr::VariantKind VarKind) const { … }

static bool isPCRel(unsigned Kind) { … }

unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
      const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
      const MCSubtargetInfo &STI) const { … }

unsigned
HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        MCSubtargetInfo const &STI) const { … }

MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
                                                MCContext &MCT) { … }

#include "HexagonGenMCCodeEmitter.inc"
llvm/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
