//===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "MCTargetDesc/MipsABIFlagsSection.h" #include "MCTargetDesc/MipsABIInfo.h" #include "MCTargetDesc/MipsBaseInfo.h" #include "MCTargetDesc/MipsMCExpr.h" #include "MCTargetDesc/MipsMCTargetDesc.h" #include "MipsTargetStreamer.h" #include "TargetInfo/MipsTargetInfo.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCAsmParserExtension.h" #include "llvm/MC/MCParser/MCAsmParserUtils.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCValue.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Alignment.h" #include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/SMLoc.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/SubtargetFeature.h" #include "llvm/TargetParser/Triple.h" #include <algorithm> #include <cassert> #include <cstdint> #include <memory> #include <string> #include <utility> usingnamespacellvm; #define DEBUG_TYPE … namespace llvm { class MCInstrInfo; } // end namespace llvm extern cl::opt<bool> EmitJalrReloc; namespace { class MipsAssemblerOptions { … }; } // end anonymous namespace const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = …; namespace { class MipsAsmParser : public MCTargetAsmParser { … }; /// MipsOperand - Instances of this class represent a parsed Mips machine /// instruction. class MipsOperand : public MCParsedAsmOperand { … }; // class MipsOperand } // end anonymous namespace static bool hasShortDelaySlot(MCInst &Inst) { … } static const MCSymbol *getSingleMCSymbol(const MCExpr *Expr) { … } static unsigned countMCSymbolRefExpr(const MCExpr *Expr) { … } static bool isEvaluated(const MCExpr *Expr) { … } static bool needsExpandMemInst(MCInst &Inst, const MCInstrDesc &MCID) { … } bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } void MipsAsmParser::onEndOfFile() { … } MipsAsmParser::MacroExpanderResultTy MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } /// Can the value be represented by a unsigned N-bit value and a shift left? template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) { … } /// Load (or add) an immediate into a register. /// /// @param ImmValue The immediate to load. /// @param DstReg The register that will hold the immediate. /// @param SrcReg A register to add to the immediate or Mips::NoRegister /// for a simple initialization. /// @param Is32BitImm Is ImmValue 32-bit or 64-bit? /// @param IsAddress True if the immediate represents an address. False if it /// is an integer. /// @param IDLoc Location of the immediate in the source file. bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg, bool Is32BitImm, bool IsAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, const MCOperand &Offset, bool Is32BitAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } // Each double-precision register DO-D15 overlaps with two of the single // precision registers F0-F31. As an example, all of the following hold true: // D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context. static unsigned nextReg(unsigned Reg) { … } // FIXME: This method is too general. In principle we should compute the number // of instructions required to synthesize the immediate inline compared to // synthesizing the address inline and relying on non .text sections. // For static O32 and N32 this may yield a small benefit, for static N64 this is // likely to yield a much larger benefit as we have to synthesize a 64bit // address to load a 64 bit value. bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym) { … } static uint64_t convertIntToDoubleImm(uint64_t ImmOp64) { … } static uint32_t covertDoubleImmToSingleImm(uint64_t ImmOp64) { … } bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad) { … } void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad) { … } bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } // Expand a integer division macro. // // Notably we don't have to emit a warning when encountering $rt as the $zero // register, or 0 as an immediate. processInstruction() has already done that. // // The destination register can only be $zero when expanding (S)DivIMacro or // D(S)DivMacro. bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, const bool IsMips64, const bool Signed) { … } bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } // Expand 'ld $<reg> offset($reg2)' to 'lw $<reg>, offset($reg2); // lw $<reg+1>>, offset+4($reg2)' // or expand 'sd $<reg> offset($reg2)' to 'sw $<reg>, offset($reg2); // sw $<reg+1>>, offset+4($reg2)' // for O32. bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad) { … } // Expand 's.d $<reg> offset($reg2)' to 'swc1 $<reg+1>, offset($reg2); // swc1 $<reg>, offset+4($reg2)' // or if little endian to 'swc1 $<reg>, offset($reg2); // swc1 $<reg+1>, offset+4($reg2)' // for Mips1. bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } // Map the DSP accumulator and control register to the corresponding gpr // operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions // do not map the DSP registers contigously to gpr registers. static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) { … } // Map the floating point register operand to the corresponding register // operand. static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) { … } // Map the coprocessor operand the corresponding gpr register operand. static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) { … } /// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing /// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits. bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { … } unsigned MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) { … } unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { … } static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, uint64_t ErrorInfo) { … } bool MipsAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { … } void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { … } void MipsAsmParser::warnIfNoMacro(SMLoc Loc) { … } void MipsAsmParser::ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands) { … } void MipsAsmParser::printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg, SMRange Range, bool ShowColors) { … } int MipsAsmParser::matchCPURegisterName(StringRef Name) { … } int MipsAsmParser::matchHWRegsRegisterName(StringRef Name) { … } int MipsAsmParser::matchFPURegisterName(StringRef Name) { … } int MipsAsmParser::matchFCCRegisterName(StringRef Name) { … } int MipsAsmParser::matchACRegisterName(StringRef Name) { … } int MipsAsmParser::matchMSA128RegisterName(StringRef Name) { … } int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) { … } bool MipsAsmParser::canUseATReg() { … } unsigned MipsAsmParser::getATReg(SMLoc Loc) { … } unsigned MipsAsmParser::getReg(int RC, int RegNo) { … } bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { … } bool MipsAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } ParseStatus MipsAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { … } ParseStatus MipsAsmParser::parseMemOperand(OperandVector &Operands) { … } bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) { … } ParseStatus MipsAsmParser::matchAnyRegisterNameWithoutDollar( OperandVector &Operands, StringRef Identifier, SMLoc S) { … } ParseStatus MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, const AsmToken &Token, SMLoc S) { … } ParseStatus MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { … } ParseStatus MipsAsmParser::parseAnyRegister(OperandVector &Operands) { … } ParseStatus MipsAsmParser::parseJumpTarget(OperandVector &Operands) { … } ParseStatus MipsAsmParser::parseInvNum(OperandVector &Operands) { … } ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) { … } /// Sometimes (i.e. load/stores) the operand may be followed immediately by /// either this. /// ::= '(', register, ')' /// handle it before we iterate so we don't get tripped up by the lack of /// a comma. bool MipsAsmParser::parseParenSuffix(StringRef Name, OperandVector &Operands) { … } /// Sometimes (i.e. in MSA) the operand may be followed immediately by /// either one of these. /// ::= '[', register, ']' /// ::= '[', integer, ']' /// handle it before we iterate so we don't get tripped up by the lack of /// a comma. bool MipsAsmParser::parseBracketSuffix(StringRef Name, OperandVector &Operands) { … } static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID = 0); bool MipsAsmParser::areEqualRegs(const MCParsedAsmOperand &Op1, const MCParsedAsmOperand &Op2) const { … } bool MipsAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { … } // FIXME: Given that these have the same name, these should both be // consistent on affecting the Parser. bool MipsAsmParser::reportParseError(const Twine &ErrorMsg) { … } bool MipsAsmParser::reportParseError(SMLoc Loc, const Twine &ErrorMsg) { … } bool MipsAsmParser::parseSetNoAtDirective() { … } bool MipsAsmParser::parseSetAtDirective() { … } bool MipsAsmParser::parseSetReorderDirective() { … } bool MipsAsmParser::parseSetNoReorderDirective() { … } bool MipsAsmParser::parseSetMacroDirective() { … } bool MipsAsmParser::parseSetNoMacroDirective() { … } bool MipsAsmParser::parseSetMsaDirective() { … } bool MipsAsmParser::parseSetNoMsaDirective() { … } bool MipsAsmParser::parseSetNoDspDirective() { … } bool MipsAsmParser::parseSetNoMips3DDirective() { … } bool MipsAsmParser::parseSetMips16Directive() { … } bool MipsAsmParser::parseSetNoMips16Directive() { … } bool MipsAsmParser::parseSetFpDirective() { … } bool MipsAsmParser::parseSetOddSPRegDirective() { … } bool MipsAsmParser::parseSetNoOddSPRegDirective() { … } bool MipsAsmParser::parseSetMtDirective() { … } bool MipsAsmParser::parseSetNoMtDirective() { … } bool MipsAsmParser::parseSetNoCRCDirective() { … } bool MipsAsmParser::parseSetNoVirtDirective() { … } bool MipsAsmParser::parseSetNoGINVDirective() { … } bool MipsAsmParser::parseSetPopDirective() { … } bool MipsAsmParser::parseSetPushDirective() { … } bool MipsAsmParser::parseSetSoftFloatDirective() { … } bool MipsAsmParser::parseSetHardFloatDirective() { … } bool MipsAsmParser::parseSetAssignment() { … } bool MipsAsmParser::parseSetMips0Directive() { … } bool MipsAsmParser::parseSetArchDirective() { … } bool MipsAsmParser::parseSetFeature(uint64_t Feature) { … } bool MipsAsmParser::eatComma(StringRef ErrorStr) { … } // Used to determine if .cpload, .cprestore, and .cpsetup have any effect. // In this class, it is only used for .cprestore. // FIXME: Only keep track of IsPicEnabled in one place, instead of in both // MipsTargetELFStreamer and MipsAsmParser. bool MipsAsmParser::isPicAndNotNxxAbi() { … } bool MipsAsmParser::parseDirectiveCpAdd(SMLoc Loc) { … } bool MipsAsmParser::parseDirectiveCpLoad(SMLoc Loc) { … } bool MipsAsmParser::parseDirectiveCpLocal(SMLoc Loc) { … } bool MipsAsmParser::parseDirectiveCpRestore(SMLoc Loc) { … } bool MipsAsmParser::parseDirectiveCPSetup() { … } bool MipsAsmParser::parseDirectiveCPReturn() { … } bool MipsAsmParser::parseDirectiveNaN() { … } bool MipsAsmParser::parseDirectiveSet() { … } /// parseDirectiveGpWord /// ::= .gpword local_sym bool MipsAsmParser::parseDirectiveGpWord() { … } /// parseDirectiveGpDWord /// ::= .gpdword local_sym bool MipsAsmParser::parseDirectiveGpDWord() { … } /// parseDirectiveDtpRelWord /// ::= .dtprelword tls_sym bool MipsAsmParser::parseDirectiveDtpRelWord() { … } /// parseDirectiveDtpRelDWord /// ::= .dtpreldword tls_sym bool MipsAsmParser::parseDirectiveDtpRelDWord() { … } /// parseDirectiveTpRelWord /// ::= .tprelword tls_sym bool MipsAsmParser::parseDirectiveTpRelWord() { … } /// parseDirectiveTpRelDWord /// ::= .tpreldword tls_sym bool MipsAsmParser::parseDirectiveTpRelDWord() { … } bool MipsAsmParser::parseDirectiveOption() { … } /// parseInsnDirective /// ::= .insn bool MipsAsmParser::parseInsnDirective() { … } /// parseRSectionDirective /// ::= .rdata bool MipsAsmParser::parseRSectionDirective(StringRef Section) { … } /// parseSSectionDirective /// ::= .sbss /// ::= .sdata bool MipsAsmParser::parseSSectionDirective(StringRef Section, unsigned Type) { … } /// parseDirectiveModule /// ::= .module oddspreg /// ::= .module nooddspreg /// ::= .module fp=value /// ::= .module softfloat /// ::= .module hardfloat /// ::= .module mt /// ::= .module crc /// ::= .module nocrc /// ::= .module virt /// ::= .module novirt /// ::= .module ginv /// ::= .module noginv bool MipsAsmParser::parseDirectiveModule() { … } /// parseDirectiveModuleFP /// ::= =32 /// ::= =xx /// ::= =64 bool MipsAsmParser::parseDirectiveModuleFP() { … } bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI, StringRef Directive) { … } bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { … } bool MipsAsmParser::parseInternalDirectiveReallowModule() { … } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmParser() { … } #define GET_REGISTER_MATCHER #define GET_MATCHER_IMPLEMENTATION #define GET_MNEMONIC_SPELL_CHECKER #include "MipsGenAsmMatcher.inc" bool MipsAsmParser::mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) { … }
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