//===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements MCELFStreamer for Mips NaCl. It emits .o object files // as required by NaCl's SFI sandbox. It inserts address-masking instructions // before dangerous control-flow and memory access instructions. It inserts // address-masking instructions after instructions that change the stack // pointer. It ensures that the mask and the dangerous instruction are always // emitted in the same bundle. It aligns call + branch delay to the bundle end, // so that return address is always aligned to the start of next bundle. // //===----------------------------------------------------------------------===// #include "Mips.h" #include "MipsELFStreamer.h" #include "MipsMCNaCl.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/Support/ErrorHandling.h" #include <cassert> usingnamespacellvm; #define DEBUG_TYPE … namespace { const unsigned IndirectBranchMaskReg = …; const unsigned LoadStoreStackMaskReg = …; /// Extend the generic MCELFStreamer class so that it can mask dangerous /// instructions. class MipsNaClELFStreamer : public MipsELFStreamer { … }; } // end anonymous namespace namespace llvm { bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, bool *IsStore) { … } bool baseRegNeedsLoadStoreMask(unsigned Reg) { … } MCELFStreamer * createMipsNaClELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB, std::unique_ptr<MCObjectWriter> OW, std::unique_ptr<MCCodeEmitter> Emitter) { … } } // end namespace llvm