llvm/llvm/lib/Target/PowerPC/PPCInstrInfo.h

//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H

#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "PPC.h"
#include "PPCRegisterInfo.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/TargetInstrInfo.h"

#define GET_INSTRINFO_HEADER
#include "PPCGenInstrInfo.inc"

namespace llvm {

// Instructions that have an immediate form might be convertible to that
// form if the correct input is a result of a load immediate. In order to
// know whether the transformation is special, we might need to know some
// of the details of the two forms.
struct ImmInstrInfo { … };

// Information required to convert an instruction to just a materialized
// immediate.
struct LoadImmediateInfo { … };

// Index into the OpcodesForSpill array.
enum SpillOpcodeKey { … };

// PPC MachineCombiner patterns
enum PPCMachineCombinerPattern : unsigned { … };

// Define list of load and store spill opcodes.
#define NoInstr …
#define Pwr8LoadOpcodes …

#define Pwr9LoadOpcodes …

#define Pwr10LoadOpcodes …

#define FutureLoadOpcodes …

#define Pwr8StoreOpcodes …

#define Pwr9StoreOpcodes …

#define Pwr10StoreOpcodes …

#define FutureStoreOpcodes …

// Initialize arrays for load and store spill opcodes on supported subtargets.
#define StoreOpcodesForSpill …
#define LoadOpcodesForSpill …

class PPCSubtarget;
class PPCInstrInfo : public PPCGenInstrInfo { … };

}

#endif