//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file contains the PowerPC implementation of the TargetInstrInfo class. // //===----------------------------------------------------------------------===// #include "PPCInstrInfo.h" #include "MCTargetDesc/PPCPredicates.h" #include "PPC.h" #include "PPCHazardRecognizers.h" #include "PPCInstrBuilder.h" #include "PPCMachineFunctionInfo.h" #include "PPCTargetMachine.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineCombinerPattern.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterPressure.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackMaps.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" usingnamespacellvm; #define DEBUG_TYPE … #define GET_INSTRMAP_INFO #define GET_INSTRINFO_CTOR_DTOR #include "PPCGenInstrInfo.inc" STATISTIC(NumStoreSPILLVSRRCAsVec, "Number of spillvsrrc spilled to stack as vec"); STATISTIC(NumStoreSPILLVSRRCAsGpr, "Number of spillvsrrc spilled to stack as gpr"); STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc"); STATISTIC(CmpIselsConverted, "Number of ISELs that depend on comparison of constants converted"); STATISTIC(MissedConvertibleImmediateInstrs, "Number of compare-immediate instructions fed by constants"); STATISTIC(NumRcRotatesConvertedToRcAnd, "Number of record-form rotates converted to record-form andi"); static cl:: opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops")); static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden); static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden); static cl::opt<bool> UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation")); static cl::opt<float> FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5), cl::desc("register pressure factor for the transformations.")); static cl::opt<bool> EnableFMARegPressureReduction( "ppc-fma-rp-reduction", cl::Hidden, cl::init(true), cl::desc("enable register pressure reduce in machine combiner pass.")); // Pin the vtable to this file. void PPCInstrInfo::anchor() { … } PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI) : … { … } /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for /// this target when scheduling the DAG. ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const { … } /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer /// to use for this target when scheduling the DAG. ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const { … } unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost) const { … } std::optional<unsigned> PPCInstrInfo::getOperandLatency( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { … } void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const { … } // This function does not list all associative and commutative operations, but // only those worth feeding through the machine combiner in an attempt to // reduce the critical path. Mostly, this means floating-point operations, // because they have high latencies(>=5) (compared to other operations, such as // and/or, which are also associative and commutative, but have low latencies). bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const { … } #define InfoArrayIdxFMAInst … #define InfoArrayIdxFAddInst … #define InfoArrayIdxFMULInst … #define InfoArrayIdxAddOpIdx … #define InfoArrayIdxMULOpIdx … #define InfoArrayIdxFSubInst … // Array keeps info for FMA instructions: // Index 0(InfoArrayIdxFMAInst): FMA instruction; // Index 1(InfoArrayIdxFAddInst): ADD instruction associated with FMA; // Index 2(InfoArrayIdxFMULInst): MUL instruction associated with FMA; // Index 3(InfoArrayIdxAddOpIdx): ADD operand index in FMA operands; // Index 4(InfoArrayIdxMULOpIdx): first MUL operand index in FMA operands; // second MUL operand index is plus 1; // Index 5(InfoArrayIdxFSubInst): SUB instruction associated with FMA. static const uint16_t FMAOpIdxInfo[][6] = …; // Check if an opcode is a FMA instruction. If it is, return the index in array // FMAOpIdxInfo. Otherwise, return -1. int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const { … } // On PowerPC target, we have two kinds of patterns related to FMA: // 1: Improve ILP. // Try to reassociate FMA chains like below: // // Pattern 1: // A = FADD X, Y (Leaf) // B = FMA A, M21, M22 (Prev) // C = FMA B, M31, M32 (Root) // --> // A = FMA X, M21, M22 // B = FMA Y, M31, M32 // C = FADD A, B // // Pattern 2: // A = FMA X, M11, M12 (Leaf) // B = FMA A, M21, M22 (Prev) // C = FMA B, M31, M32 (Root) // --> // A = FMUL M11, M12 // B = FMA X, M21, M22 // D = FMA A, M31, M32 // C = FADD B, D // // breaking the dependency between A and B, allowing FMA to be executed in // parallel (or back-to-back in a pipeline) instead of depending on each other. // // 2: Reduce register pressure. // Try to reassociate FMA with FSUB and a constant like below: // C is a floating point const. // // Pattern 1: // A = FSUB X, Y (Leaf) // D = FMA B, C, A (Root) // --> // A = FMA B, Y, -C // D = FMA A, X, C // // Pattern 2: // A = FSUB X, Y (Leaf) // D = FMA B, A, C (Root) // --> // A = FMA B, Y, -C // D = FMA A, X, C // // Before the transformation, A must be assigned with different hardware // register with D. After the transformation, A and D must be assigned with // same hardware register due to TIE attribute of FMA instructions. // bool PPCInstrInfo::getFMAPatterns(MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns, bool DoRegPressureReduce) const { … } void PPCInstrInfo::finalizeInsInstrs( MachineInstr &Root, unsigned &Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs) const { … } bool PPCInstrInfo::shouldReduceRegisterPressure( const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const { … } bool PPCInstrInfo::isLoadFromConstantPool(MachineInstr *I) const { … } Register PPCInstrInfo::generateLoadForNewConst( unsigned Idx, MachineInstr *MI, Type *Ty, SmallVectorImpl<MachineInstr *> &InsInstrs) const { … } // This function returns the const value in constant pool if the \p I is a load // from constant pool. const Constant * PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const { … } CombinerObjective PPCInstrInfo::getCombinerObjective(unsigned Pattern) const { … } bool PPCInstrInfo::getMachineCombinerPatterns( MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns, bool DoRegPressureReduce) const { … } void PPCInstrInfo::genAlternativeCodeSequence( MachineInstr &Root, unsigned Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const { … } void PPCInstrInfo::reassociateFMA( MachineInstr &Root, unsigned Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const { … } // Detect 32 -> 64-bit extensions where we may reuse the low sub-register. bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const { … } Register PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { … } // For opcodes with the ReMaterializable flag set, this function is called to // verify the instruction is really rematable. bool PPCInstrInfo::isReallyTriviallyReMaterializable( const MachineInstr &MI) const { … } Register PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { … } MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const { … } bool PPCInstrInfo::findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const { … } void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { … } /// Return the noop instruction to use for a noop. MCInst PPCInstrInfo::getNop() const { … } // Branch analysis. // Note: If the condition register is set to CTR or CTR8 then this is a // BDNZ (imm == 1) or BDZ (imm == 0) branch. bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { … } unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { … } unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { … } // Select analysis. bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const { … } void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &dl, Register DestReg, ArrayRef<MachineOperand> Cond, Register TrueReg, Register FalseReg) const { … } static unsigned getCRBitValue(unsigned CRBit) { … } void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest, bool RenamableSrc) const { … } unsigned PPCInstrInfo::getSpillIndex(const TargetRegisterClass *RC) const { … } unsigned PPCInstrInfo::getStoreOpcodeForSpill(const TargetRegisterClass *RC) const { … } unsigned PPCInstrInfo::getLoadOpcodeForSpill(const TargetRegisterClass *RC) const { … } void PPCInstrInfo::StoreRegToStackSlot( MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const { … } void PPCInstrInfo::storeRegToStackSlotNoUpd( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { … } void PPCInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const { … } void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const { … } void PPCInstrInfo::loadRegFromStackSlotNoUpd( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { … } void PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const { … } bool PPCInstrInfo:: reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { … } // For some instructions, it is legal to fold ZERO into the RA register field. // This function performs that fold by replacing the operand with PPC::ZERO, // it does not consider whether the load immediate zero is no longer in use. bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const { … } // Folds zero into instructions which have a load immediate zero as an operand // but also recognize zero as immediate zero. If the definition of the load // has no more users it is deleted. bool PPCInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const { … } static bool MBBDefinesCTR(MachineBasicBlock &MBB) { … } // We should make sure that, if we're going to predicate both sides of a // condition (a diamond), that both sides don't define the counter register. We // can predicate counter-decrement-based branches, but while that predicates // the branching, it does not predicate the counter decrement. If we tried to // merge the triangle into one predicated block, we'd decrement the counter // twice. bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const { … } bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const { … } bool PPCInstrInfo::isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const { … } bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI, ArrayRef<MachineOperand> Pred) const { … } bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, ArrayRef<MachineOperand> Pred2) const { … } bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, bool SkipDead) const { … } bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const { … } bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const { … } bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const { … } bool PPCInstrInfo::getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const { … } static bool isLdStSafeToCluster(const MachineInstr &LdSt, const TargetRegisterInfo *TRI) { … } // Only cluster instruction pair that have the same opcode, and they are // clusterable according to PowerPC specification. static bool isClusterableLdStOpcPair(unsigned FirstOpc, unsigned SecondOpc, const PPCSubtarget &Subtarget) { … } bool PPCInstrInfo::shouldClusterMemOps( ArrayRef<const MachineOperand *> BaseOps1, int64_t OpOffset1, bool OffsetIsScalable1, ArrayRef<const MachineOperand *> BaseOps2, int64_t OpOffset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const { … } /// GetInstSize - Return the number of bytes of code the specified /// instruction may be. This returns the maximum number of bytes. /// unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { … } std::pair<unsigned, unsigned> PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { … } ArrayRef<std::pair<unsigned, const char *>> PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { … } // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. // The VSX versions have the advantage of a full 64-register target whereas // the FP ones have the advantage of lower latency and higher throughput. So // what we are after is using the faster instructions in low register pressure // situations and using the larger register file in high register pressure // situations. bool PPCInstrInfo::expandVSXMemPseudo(MachineInstr &MI) const { … } static bool isAnImmediateOperand(const MachineOperand &MO) { … } bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { … } // Essentially a compile-time implementation of a compare->isel sequence. // It takes two constants to compare, along with the true/false registers // and the comparison type (as a subreg to a CR field) and returns one // of the true/false registers, depending on the comparison results. static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg) { … } void PPCInstrInfo::replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const { … } // Replace an instruction with one that materializes a constant (and sets // CR0 if the original instruction was a record-form instruction). void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const { … } MachineInstr *PPCInstrInfo::getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const { … } void PPCInstrInfo::materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const { … } MachineInstr *PPCInstrInfo::getForwardingDefMI( MachineInstr &MI, unsigned &OpNoForForwarding, bool &SeenIntermediateUse) const { … } unsigned PPCInstrInfo::getSpillTarget() const { … } ArrayRef<unsigned> PPCInstrInfo::getStoreOpcodesForSpillArray() const { … } ArrayRef<unsigned> PPCInstrInfo::getLoadOpcodesForSpillArray() const { … } // This opt tries to convert the following imm form to an index form to save an // add for stack variables. // Return false if no such pattern found. // // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi // ADD instr: ToBeDeletedReg = ADD ToBeChangedReg(killed), ScaleReg // Imm instr: Reg = op OffsetImm, ToBeDeletedReg(killed) // // can be converted to: // // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, (OffsetAddi + OffsetImm) // Index instr: Reg = opx ScaleReg, ToBeChangedReg(killed) // // In order to eliminate ADD instr, make sure that: // 1: (OffsetAddi + OffsetImm) must be int16 since this offset will be used in // new ADDI instr and ADDI can only take int16 Imm. // 2: ToBeChangedReg must be killed in ADD instr and there is no other use // between ADDI and ADD instr since its original def in ADDI will be changed // in new ADDI instr. And also there should be no new def for it between // ADD and Imm instr as ToBeChangedReg will be used in Index instr. // 3: ToBeDeletedReg must be killed in Imm instr and there is no other use // between ADD and Imm instr since ADD instr will be eliminated. // 4: ScaleReg must not be redefined between ADD and Imm instr since it will be // moved to Index instr. bool PPCInstrInfo::foldFrameOffset(MachineInstr &MI) const { … } bool PPCInstrInfo::isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const { … } bool PPCInstrInfo::isADDInstrEligibleForFolding(MachineInstr &ADDMI) const { … } bool PPCInstrInfo::isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &ToBeDeletedReg, unsigned &XFormOpcode, int64_t &OffsetImm, ImmInstrInfo &III) const { … } bool PPCInstrInfo::isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const { … } // If this instruction has an immediate form and one of its operands is a // result of a load-immediate or an add-immediate, convert it to // the immediate form if the constant is in range. bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, SmallSet<Register, 4> &RegsToUpdate, MachineInstr **KilledDef) const { … } bool PPCInstrInfo::combineRLWINM(MachineInstr &MI, MachineInstr **ToErase) const { … } bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const { … } // Utility function for swaping two arbitrary operands of an instruction. static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) { … } // Check if the 'MI' that has the index OpNoForForwarding // meets the requirement described in the ImmInstrInfo. bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding ) const { … } // Check if the DefMI is the add inst and set the ImmMO and RegMO // accordingly. bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI, const ImmInstrInfo &III, MachineOperand *&ImmMO, MachineOperand *&RegMO) const { … } bool PPCInstrInfo::isRegElgibleForForwarding( const MachineOperand &RegMO, const MachineInstr &DefMI, const MachineInstr &MI, bool KillDefMI, bool &IsFwdFeederRegKilled, bool &SeenIntermediateUse) const { … } bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO, const MachineInstr &DefMI, const ImmInstrInfo &III, int64_t &Imm, int64_t BaseImm) const { … } bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, unsigned OpNoForForwarding, MachineInstr **KilledDef) const { … } bool PPCInstrInfo::transformToNewImmFormFedByAdd( MachineInstr &MI, MachineInstr &DefMI, unsigned OpNoForForwarding) const { … } // If an X-Form instruction is fed by an add-immediate and one of its operands // is the literal zero, attempt to forward the source of the add-immediate to // the corresponding D-Form instruction with the displacement coming from // the immediate being added. bool PPCInstrInfo::transformToImmFormFedByAdd( MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding, MachineInstr &DefMI, bool KillDefMI) const { … } bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, unsigned ConstantOpNo, MachineInstr &DefMI) const { … } const TargetRegisterClass * PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const { … } int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) { … } static bool isOpZeroOfSubwordPreincLoad(int Opcode) { … } // This function checks for sign extension from 32 bits to 64 bits. static bool definedBySignExtendingOp(const unsigned Reg, const MachineRegisterInfo *MRI) { … } // This function checks the machine instruction that defines the input register // Reg. If that machine instruction always outputs a value that has only zeros // in the higher 32 bits then this function will return true. static bool definedByZeroExtendingOp(const unsigned Reg, const MachineRegisterInfo *MRI) { … } // This function returns true if the input MachineInstr is a TOC save // instruction. bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const { … } // We limit the max depth to track incoming values of PHIs or binary ops // (e.g. AND) to avoid excessive cost. const unsigned MAX_BINOP_DEPTH = …; // The isSignOrZeroExtended function is recursive. The parameter BinOpDepth // does not count all of the recursions. The parameter BinOpDepth is incremented // only when isSignOrZeroExtended calls itself more than once. This is done to // prevent expontential recursion. There is no parameter to track linear // recursion. std::pair<bool, bool> PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const { … } bool PPCInstrInfo::isBDNZ(unsigned Opcode) const { … } namespace { class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo { … }; } // namespace std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> PPCInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const { … } MachineInstr *PPCInstrInfo::findLoopInstr( MachineBasicBlock &PreHeader, SmallPtrSet<MachineBasicBlock *, 8> &Visited) const { … } // Return true if get the base operand, byte offset of an instruction and the // memory width. Width is the size of memory that is being loaded/stored. bool PPCInstrInfo::getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const { … } bool PPCInstrInfo::areMemAccessesTriviallyDisjoint( const MachineInstr &MIa, const MachineInstr &MIb) const { … }
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