llvm/llvm/lib/Target/RISCV/RISCVInstrInfo.h

//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the RISC-V implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H

#include "RISCV.h"
#include "RISCVRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DiagnosticInfo.h"

#define GET_INSTRINFO_HEADER
#define GET_INSTRINFO_OPERAND_ENUM
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenRegisterInfo.inc"

namespace llvm {

class RISCVSubtarget;

static const MachineMemOperand::Flags MONontemporalBit0 = …;
static const MachineMemOperand::Flags MONontemporalBit1 = …;

namespace RISCVCC {

enum CondCode { … };

CondCode getOppositeBranchCondition(CondCode);
unsigned getBrCond(CondCode CC, bool Imm = false);

} // end of namespace RISCVCC

// RISCV MachineCombiner patterns
enum RISCVMachineCombinerPattern : unsigned { … };

class RISCVInstrInfo : public RISCVGenInstrInfo { … };

namespace RISCV {

// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
bool isSEXT_W(const MachineInstr &MI);
bool isZEXT_W(const MachineInstr &MI);
bool isZEXT_B(const MachineInstr &MI);

// Returns true if the given MI is an RVV instruction opcode for which we may
// expect to see a FrameIndex operand.
bool isRVVSpill(const MachineInstr &MI);

std::optional<std::pair<unsigned, unsigned>>
isRVVSpillForZvlsseg(unsigned Opcode);

bool isFaultFirstLoad(const MachineInstr &MI);

// Implemented in RISCVGenInstrInfo.inc
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);

// Return true if both input instructions have equal rounding mode. If at least
// one of the instructions does not have rounding mode, false will be returned.
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);

// If \p Opcode is a .vx vector instruction, returns the lower number of bits
// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
// returns null.
std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
                                                       unsigned Log2SEW);

// Returns the MC opcode of RVV pseudo instruction.
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);

// For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
// the log2 EEW of the destination operand.
unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);

// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
static constexpr int64_t VLMaxSentinel = …;

// Mask assignments for floating-point
static constexpr unsigned FPMASK_Negative_Infinity = …;
static constexpr unsigned FPMASK_Negative_Normal = …;
static constexpr unsigned FPMASK_Negative_Subnormal = …;
static constexpr unsigned FPMASK_Negative_Zero = …;
static constexpr unsigned FPMASK_Positive_Zero = …;
static constexpr unsigned FPMASK_Positive_Subnormal = …;
static constexpr unsigned FPMASK_Positive_Normal = …;
static constexpr unsigned FPMASK_Positive_Infinity = …;
static constexpr unsigned FPMASK_Signaling_NaN = …;
static constexpr unsigned FPMASK_Quiet_NaN = …;
} // namespace RISCV

namespace RISCVVPseudosTable {

struct PseudoInfo { … };

#define GET_RISCVVPseudosTable_DECL
#include "RISCVGenSearchableTables.inc"

} // end namespace RISCVVPseudosTable

namespace RISCV {

struct RISCVMaskedPseudoInfo { … };
#define GET_RISCVMaskedPseudosTable_DECL
#include "RISCVGenSearchableTables.inc"
} // end namespace RISCV

} // end namespace llvm
#endif