llvm/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp

//===-- RISCVInsertWriteVXRM.cpp - Insert Write of RISC-V VXRM CSR --------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This pass inserts writes to the VXRM CSR as needed by vector instructions.
// Each instruction that uses VXRM carries an operand that contains its required
// VXRM value. This pass tries to optimize placement to avoid redundant writes
// to VXRM.
//
// This is done using 2 dataflow algorithms. The first is a forward data flow
// to calculate where a VXRM value is available. The second is a backwards
// dataflow to determine where a VXRM value is anticipated.
//
// Finally, we use the results of these two dataflows to insert VXRM writes
// where a value is anticipated, but not available.
//
// FIXME: This pass does not split critical edges, so there can still be some
// redundancy.
//
// FIXME: If we are willing to have writes that aren't always needed, we could
// reduce the number of VXRM writes in some cases.
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include <queue>

usingnamespacellvm;

#define DEBUG_TYPE …
#define RISCV_INSERT_WRITE_VXRM_NAME …

namespace {

class VXRMInfo { … };

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_ATTRIBUTE_USED
inline raw_ostream &operator<<(raw_ostream &OS, const VXRMInfo &V) {
  V.print(OS);
  return OS;
}
#endif

struct BlockData { … };

class RISCVInsertWriteVXRM : public MachineFunctionPass { … };

} // end anonymous namespace

char RISCVInsertWriteVXRM::ID = …;

INITIALIZE_PASS(…)

static bool ignoresVXRM(const MachineInstr &MI) { … }

bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) { … }

void RISCVInsertWriteVXRM::computeAvailable(const MachineBasicBlock &MBB) { … }

void RISCVInsertWriteVXRM::computeAnticipated(const MachineBasicBlock &MBB) { … }

void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) { … }

bool RISCVInsertWriteVXRM::runOnMachineFunction(MachineFunction &MF) { … }

FunctionPass *llvm::createRISCVInsertWriteVXRMPass() { … }