//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements the interfaces that Sparc uses to lower LLVM code into a // selection DAG. // //===----------------------------------------------------------------------===// #include "SparcISelLowering.h" #include "MCTargetDesc/SparcMCExpr.h" #include "MCTargetDesc/SparcMCTargetDesc.h" #include "SparcMachineFunctionInfo.h" #include "SparcRegisterInfo.h" #include "SparcTargetMachine.h" #include "SparcTargetObjectFile.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/Function.h" #include "llvm/IR/Module.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/KnownBits.h" usingnamespacellvm; //===----------------------------------------------------------------------===// // Calling Convention Implementation //===----------------------------------------------------------------------===// static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } // Allocate a full-sized argument for the 64-bit ABI. static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } // Allocate a half-sized argument for the 64-bit ABI. // // This is used when passing { float, int } structs by value in registers. static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } #include "SparcGenCallingConv.inc" // The calling conventions in SparcCallingConv.td are described in terms of the // callee's register window. This function translates registers to the // corresponding caller window %o register. static unsigned toCallerWindow(unsigned Reg) { … } bool SparcTargetLowering::CanLowerReturn( CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { … } SDValue SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { … } // Lower return values for the 64-bit ABI. // Return values are passed the exactly the same way as function arguments. SDValue SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { … } /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are /// passed in either one or two GPRs, including FP values. TODO: we should /// pass FP values in FP registers for fastcc functions. SDValue SparcTargetLowering::LowerFormalArguments_32( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { … } // Lower formal arguments for the 64 bit ABI. SDValue SparcTargetLowering::LowerFormalArguments_64( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { … } // Check whether any of the argument registers are reserved static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI, const MachineFunction &MF) { … } static void emitReservedArgRegCallError(const MachineFunction &MF) { … } SDValue SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const { … } static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call) { … } /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. bool SparcTargetLowering::IsEligibleForTailCallOptimization( CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const { … } // Lower a call for the 32-bit ABI. SDValue SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const { … } // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const { … } // Fixup floating point arguments in the ... part of a varargs call. // // The SPARC v9 ABI requires that floating point arguments are treated the same // as integers when calling a varargs function. This does not apply to the // fixed arguments that are part of the function's prototype. // // This function post-processes a CCValAssign array created by // AnalyzeCallOperands(). static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, ArrayRef<ISD::OutputArg> Outs) { … } // Lower a call for the 64-bit ABI. SDValue SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const { … } //===----------------------------------------------------------------------===// // TargetLowering Implementation //===----------------------------------------------------------------------===// TargetLowering::AtomicExpansionKind SparcTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { … } /// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC /// rcond condition. static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) { … } /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC /// condition. static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { … } /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC /// FCC condition. static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { … } SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI) : … { … } bool SparcTargetLowering::useSoftFloat() const { … } const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { … } EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const { … } /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. void SparcTargetLowering::computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { … } // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC) { … } // Convert to a target node and set target flags. SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const { … } // Split Op into high and low parts according to HiTF and LoTF. // Return an ADD node combining the parts. SDValue SparcTargetLowering::makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const { … } // Build SDNodes for producing an address from a GlobalAddress, ConstantPool, // or ExternalSymbol SDNode. SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const { … } SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const { … } static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) { … } static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) { … } static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) { … } static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) { … } static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) { … } static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) { … } static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit) { … } static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit) { … } static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) { … } static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { … } static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) { … } static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { … } static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush = false) { … } static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) { … } static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) { … } static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode) { … } // Lower a f128 load into two f64 loads. static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) { … } static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) { … } // Lower a f128 store into two f64 stores. static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { … } static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) { … } static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { … } static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) { … } SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, SelectionDAG &DAG) const { … } SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const { … } SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { … } MachineBasicBlock * SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { … } MachineBasicBlock * SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const { … } //===----------------------------------------------------------------------===// // Sparc Inline Assembly Support //===----------------------------------------------------------------------===// /// getConstraintType - Given a constraint letter, return the type of /// constraint it is for this target. SparcTargetLowering::ConstraintType SparcTargetLowering::getConstraintType(StringRef Constraint) const { … } TargetLowering::ConstraintWeight SparcTargetLowering:: getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const { … } /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void SparcTargetLowering::LowerAsmOperandForConstraint( SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const { … } std::pair<unsigned, const TargetRegisterClass *> SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { … } bool SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { … } void SparcTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>& Results, SelectionDAG &DAG) const { … } // Override to enable LOAD_STACK_GUARD lowering on Linux. bool SparcTargetLowering::useLoadStackGuardNode() const { … } // Override to disable global variable loading on Linux. void SparcTargetLowering::insertSSPDeclarations(Module &M) const { … } void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const { … }
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