X86BaseInfo.h | Explore in Territory

//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the X86 target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H

#include "X86MCTargetDesc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/ErrorHandling.h"

namespace llvm {
namespace X86 {
// Enums for memory operand decoding. Each memory operand is represented with
// a 5 operand sequence in the form: [Base, Scale, Index, Disp, Segment]
enum { … };

/// AVX512 static rounding constants. These need to match the values in
/// avx512fintrin.h.
enum STATIC_ROUNDING { … };

/// The constants to describe instr prefixes if there are
enum IPREFIXES { … };

enum OperandType : unsigned { … };

// X86 specific condition code. These correspond to X86_*_COND in
// X86InstrInfo.td. They must be kept in synch.
enum CondCode { … };

// The classification for the first instruction in macro fusion.
// FIXME: Zen 3 support branch fusion for OR/XOR.
enum class FirstMacroFusionInstKind { … };

enum class SecondMacroFusionInstKind { … };

/// \returns the type of the first instruction in macro-fusion.
// FIXME: Zen 3 support branch fusion for OR/XOR.
inline FirstMacroFusionInstKind
classifyFirstOpcodeInMacroFusion(unsigned Opcode) { … }

/// \returns the type of the second instruction in macro-fusion.
inline SecondMacroFusionInstKind
classifySecondCondCodeInMacroFusion(X86::CondCode CC) { … }

/// \param FirstKind kind of the first instruction in macro fusion.
/// \param SecondKind kind of the second instruction in macro fusion.
///
/// \returns true if the two instruction can be macro fused.
inline bool isMacroFused(FirstMacroFusionInstKind FirstKind,
                         SecondMacroFusionInstKind SecondKind) { … }

/// Defines the possible values of the branch boundary alignment mask.
enum AlignBranchBoundaryKind : uint8_t { … };

/// Defines the encoding values for segment override prefix.
enum EncodingOfSegmentOverridePrefix : uint8_t { … };

/// Given a segment register, return the encoding of the segment override
/// prefix for it.
inline EncodingOfSegmentOverridePrefix
getSegmentOverridePrefixForReg(MCRegister Reg) { … }

} // namespace X86

/// X86II - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
namespace X86II {
/// Target Operand Flag enum.
enum TOF { … };

enum : uint64_t { … };

/// \returns true if the instruction with given opcode is a prefix.
inline bool isPrefix(uint64_t TSFlags) { … }

/// \returns true if the instruction with given opcode is a pseudo.
inline bool isPseudo(uint64_t TSFlags) { … }

/// \returns the "base" X86 opcode for the specified machine
/// instruction.
inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { … }

inline bool hasImm(uint64_t TSFlags) { … }

/// Decode the "size of immediate" field from the TSFlags field of the
/// specified instruction.
inline unsigned getSizeOfImm(uint64_t TSFlags) { … }

/// \returns true if the immediate of the specified instruction's TSFlags
/// indicates that it is pc relative.
inline bool isImmPCRel(uint64_t TSFlags) { … }

/// \returns true if the immediate of the specified instruction's
/// TSFlags indicates that it is signed.
inline bool isImmSigned(uint64_t TSFlags) { … }

/// Compute whether all of the def operands are repeated in the uses and
/// therefore should be skipped.
/// This determines the start of the unique operand list. We need to determine
/// if all of the defs have a corresponding tied operand in the uses.
/// Unfortunately, the tied operand information is encoded in the uses not
/// the defs so we have to use some heuristics to find which operands to
/// query.
inline unsigned getOperandBias(const MCInstrDesc &Desc) { … }

/// \returns true if the instruction has a NDD (new data destination).
inline bool hasNewDataDest(uint64_t TSFlags) { … }

/// \returns operand # for the first field of the memory operand or -1 if no
/// memory operands.
/// NOTE: This ignores tied operands.  If there is a tied register which is
/// duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only counted
/// as one operand.
inline int getMemoryOperandNo(uint64_t TSFlags) { … }

/// \returns true if the register is a XMM.
inline bool isXMMReg(MCRegister Reg) { … }

/// \returns true if the register is a YMM.
inline bool isYMMReg(MCRegister Reg) { … }

/// \returns true if the register is a ZMM.
inline bool isZMMReg(MCRegister Reg) { … }

/// \returns true if \p Reg is an apx extended register.
inline bool isApxExtendedReg(MCRegister Reg) { … }

/// \returns true if the MachineOperand is a x86-64 extended (r8 or
/// higher) register,  e.g. r8, xmm8, xmm13, etc.
inline bool isX86_64ExtendedReg(MCRegister Reg) { … }

inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) { … }

/// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
/// registers, e.g. zmm21, etc.
static inline bool is32ExtendedReg(MCRegister Reg) { … }

inline bool isX86_64NonExtLowByteReg(MCRegister Reg) { … }

/// \returns true if this is a masked instruction.
inline bool isKMasked(uint64_t TSFlags) { … }

/// \returns true if this is a merge masked instruction.
inline bool isKMergeMasked(uint64_t TSFlags) { … }

/// \returns true if the intruction needs a SIB.
inline bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode) { … }

} // namespace X86II
} // namespace llvm
#endif
llvm/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
