llvm/llvm/lib/Target/X86/X86InstrInfo.h

//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H

#include "MCTargetDesc/X86BaseInfo.h"
#include "X86InstrFMA3Info.h"
#include "X86RegisterInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include <vector>

#define GET_INSTRINFO_HEADER
#include "X86GenInstrInfo.inc"

namespace llvm {
class X86Subtarget;

// X86 MachineCombiner patterns
enum X86MachineCombinerPattern : unsigned { … };

namespace X86 {

enum AsmComments { … };

/// Return a pair of condition code for the given predicate and whether
/// the instruction operands should be swaped to match the condition code.
std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);

/// Return a cmov opcode for the given register size in bytes, and operand type.
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
                       bool HasNDD = false);

/// Return the source operand # for condition code by \p MCID. If the
/// instruction doesn't have a condition code, return -1.
int getCondSrcNoFromDesc(const MCInstrDesc &MCID);

/// Return the condition code of the instruction. If the instruction doesn't
/// have a condition code, return X86::COND_INVALID.
CondCode getCondFromMI(const MachineInstr &MI);

// Turn JCC instruction into condition code.
CondCode getCondFromBranch(const MachineInstr &MI);

// Turn SETCC instruction into condition code.
CondCode getCondFromSETCC(const MachineInstr &MI);

// Turn CMOV instruction into condition code.
CondCode getCondFromCMov(const MachineInstr &MI);

// Turn CFCMOV instruction into condition code.
CondCode getCondFromCFCMov(const MachineInstr &MI);

// Turn CCMP instruction into condition code.
CondCode getCondFromCCMP(const MachineInstr &MI);

// Turn condition code into condition flags for CCMP/CTEST.
int getCCMPCondFlagsFromCondCode(CondCode CC);

// Get the opcode of corresponding NF variant.
unsigned getNFVariant(unsigned Opc);

// Get the opcode of corresponding NonND variant.
unsigned getNonNDVariant(unsigned Opc);

/// GetOppositeBranchCondition - Return the inverse of the specified cond,
/// e.g. turning COND_E to COND_NE.
CondCode GetOppositeBranchCondition(CondCode CC);

/// Get the VPCMP immediate for the given condition.
unsigned getVPCMPImmForCond(ISD::CondCode CC);

/// Get the VPCMP immediate if the opcodes are swapped.
unsigned getSwappedVPCMPImm(unsigned Imm);

/// Get the VPCOM immediate if the opcodes are swapped.
unsigned getSwappedVPCOMImm(unsigned Imm);

/// Get the VCMP immediate if the opcodes are swapped.
unsigned getSwappedVCMPImm(unsigned Imm);

/// Get the width of the vector register operand.
unsigned getVectorRegisterWidth(const MCOperandInfo &Info);

/// Check if the instruction is X87 instruction.
bool isX87Instruction(MachineInstr &MI);

/// Return the index of the instruction's first address operand, if it has a
/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(),
/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as
/// real instructions (e.g., JMP64m).
int getFirstAddrOperandIdx(const MachineInstr &MI);

/// Find any constant pool entry associated with a specific instruction operand.
const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);

} // namespace X86

/// isGlobalStubReference - Return true if the specified TargetFlag operand is
/// a reference to a stub for a global, not the global itself.
inline static bool isGlobalStubReference(unsigned char TargetFlag) { … }

/// isGlobalRelativeToPICBase - Return true if the specified global value
/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg).  If this
/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { … }

inline static bool isScale(const MachineOperand &MO) { … }

inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { … }

inline static bool isMem(const MachineInstr &MI, unsigned Op) { … }

class X86InstrInfo final : public X86GenInstrInfo { … };
} // namespace llvm

#endif