//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "MCTargetDesc/X86BaseInfo.h" #include "MCTargetDesc/X86EncodingOptimization.h" #include "MCTargetDesc/X86IntelInstPrinter.h" #include "MCTargetDesc/X86MCExpr.h" #include "MCTargetDesc/X86MCTargetDesc.h" #include "MCTargetDesc/X86TargetStreamer.h" #include "TargetInfo/X86TargetInfo.h" #include "X86AsmParserCommon.h" #include "X86Operand.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> #include <memory> usingnamespacellvm; static cl::opt<bool> LVIInlineAsmHardening( "x86-experimental-lvi-inline-asm-hardening", cl::desc("Harden inline assembly code that may be vulnerable to Load Value" " Injection (LVI). This feature is experimental."), cl::Hidden); static bool checkScale(unsigned Scale, StringRef &ErrMsg) { … } namespace { // Including the generated SSE2AVX compression tables. #define GET_X86_SSE2AVX_TABLE #include "X86GenInstrMapping.inc" static const char OpPrecedence[] = …; class X86AsmParser : public MCTargetAsmParser { … }; } // end anonymous namespace #define GET_REGISTER_MATCHER #define GET_SUBTARGET_FEATURE_NAME #include "X86GenAsmMatcher.inc" static bool CheckBaseRegAndIndexRegAndScale(MCRegister BaseReg, MCRegister IndexReg, unsigned Scale, bool Is64BitMode, StringRef &ErrMsg) { … } bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName, SMLoc StartLoc, SMLoc EndLoc) { … } bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, bool RestoreOnFailure) { … } bool X86AsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } ParseStatus X86AsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) { … } std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) { … } bool X86AsmParser::IsSIReg(MCRegister Reg) { … } MCRegister X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg) { … } void X86AsmParser::AddDefaultSrcDestOperands( OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) { … } bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands, OperandVector &FinalOperands) { … } bool X86AsmParser::parseOperand(OperandVector &Operands, StringRef Name) { … } bool X86AsmParser::CreateMemForMSInlineAsm( MCRegister SegReg, const MCExpr *Disp, MCRegister BaseReg, MCRegister IndexReg, unsigned Scale, bool NonAbsMem, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, const InlineAsmIdentifierInfo &Info, OperandVector &Operands) { … } // Some binary bitwise operators have a named synonymous // Query a candidate string for being such a named operator // and if so - invoke the appropriate handler bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM, bool &ParseError, SMLoc &End) { … } bool X86AsmParser::ParseMasmNamedOperator(StringRef Name, IntelExprStateMachine &SM, bool &ParseError, SMLoc &End) { … } // Check if current intel expression append after an operand. // Like: [Operand][Intel Expression] void X86AsmParser::tryParseOperandIdx(AsmToken::TokenKind PrevTK, IntelExprStateMachine &SM) { … } bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { … } void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start, SMLoc End) { … } // Inline assembly may use variable names with namespace alias qualifiers. bool X86AsmParser::ParseIntelInlineAsmIdentifier( const MCExpr *&Val, StringRef &Identifier, InlineAsmIdentifierInfo &Info, bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator) { … } //ParseRoundingModeOp - Parse AVX-512 rounding mode operand bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) { … } /// Parse condtional flags for CCMP/CTEST, e.g {dfv=of,sf,zf,cf} right after /// mnemonic. bool X86AsmParser::parseCFlagsOp(OperandVector &Operands) { … } /// Parse the '.' operator. bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) { … } /// Parse the 'offset' operator. /// This operator is used to specify the location of a given operand bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID, InlineAsmIdentifierInfo &Info, SMLoc &End) { … } // Query a candidate string for being an Intel assembly operator // Report back its kind, or IOK_INVALID if does not evaluated as a known one unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) { … } /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator /// returns the number of elements in an array. It returns the value 1 for /// non-array variables. The SIZE operator returns the size of a C or C++ /// variable. A variable's size is the product of its LENGTH and TYPE. The /// TYPE operator returns the size of a C or C++ type or variable. If the /// variable is an array, TYPE returns the size of a single element. unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) { … } // Query a candidate string for being an Intel assembly operator // Report back its kind, or IOK_INVALID if does not evaluated as a known one unsigned X86AsmParser::IdentifyMasmOperator(StringRef Name) { … } /// Parse the 'LENGTHOF', 'SIZEOF', and 'TYPE' operators. The LENGTHOF operator /// returns the number of elements in an array. It returns the value 1 for /// non-array variables. The SIZEOF operator returns the size of a type or /// variable in bytes. A variable's size is the product of its LENGTH and TYPE. /// The TYPE operator returns the size of a variable. If the variable is an /// array, TYPE returns the size of a single element. bool X86AsmParser::ParseMasmOperator(unsigned OpKind, int64_t &Val) { … } bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) { … } bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) { … } bool X86AsmParser::parseATTOperand(OperandVector &Operands) { … } // X86::COND_INVALID if not a recognized condition code or alternate mnemonic, // otherwise the EFLAGS Condition Code enumerator. X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) { … } // true on failure, false otherwise // If no {z} mark was found - Parser doesn't advance bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc) { … } // true on failure, false otherwise bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) { … } /// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix /// has already been parsed if present. disp may be provided as well. bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, OperandVector &Operands) { … } // Parse either a standard primary expression or a register. bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) { … } bool X86AsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { … } static bool convertSSEToAVX(MCInst &Inst) { … } bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) { … } bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) { … } void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) { … } /// RET instructions and also instructions that indirect calls/jumps from memory /// combine a load and a branch within a single instruction. To mitigate these /// instructions against LVI, they must be decomposed into separate load and /// branch instructions, with an LFENCE in between. For more details, see: /// - X86LoadValueInjectionRetHardening.cpp /// - X86LoadValueInjectionIndirectThunks.cpp /// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection /// /// Returns `true` if a mitigation was applied or warning was emitted. void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) { … } /// To mitigate LVI, every instruction that performs a load can be followed by /// an LFENCE instruction to squash any potential mis-speculation. There are /// some instructions that require additional considerations, and may requre /// manual mitigation. For more details, see: /// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection /// /// Returns `true` if a mitigation was applied or warning was emitted. void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst, MCStreamer &Out) { … } void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out) { … } static unsigned getPrefixes(OperandVector &Operands) { … } bool X86AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { … } void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands, MCStreamer &Out, bool MatchingInlineAsm) { … } bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures, bool MatchingInlineAsm) { … } unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) { … } bool X86AsmParser::matchAndEmitATTInstruction( SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { … } bool X86AsmParser::matchAndEmitIntelInstruction( SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { … } bool X86AsmParser::omitRegisterFromClobberLists(MCRegister Reg) { … } bool X86AsmParser::ParseDirective(AsmToken DirectiveID) { … } bool X86AsmParser::parseDirectiveArch() { … } /// parseDirectiveNops /// ::= .nops size[, control] bool X86AsmParser::parseDirectiveNops(SMLoc L) { … } /// parseDirectiveEven /// ::= .even bool X86AsmParser::parseDirectiveEven(SMLoc L) { … } /// ParseDirectiveCode /// ::= .code16 | .code32 | .code64 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) { … } // .cv_fpo_proc foo bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) { … } // .cv_fpo_setframe ebp bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) { … } // .cv_fpo_pushreg ebx bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) { … } // .cv_fpo_stackalloc 20 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) { … } // .cv_fpo_stackalign 8 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) { … } // .cv_fpo_endprologue bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) { … } // .cv_fpo_endproc bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) { … } bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo) { … } bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) { … } bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) { … } bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) { … } bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) { … } bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) { … } // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86AsmParser() { … } #define GET_MATCHER_IMPLEMENTATION #include "X86GenAsmMatcher.inc"
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