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llvm/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c 

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN:   -target-feature +zvfhmin -disable-O0-optnone  \
// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN:   FileCheck --check-prefix=CHECK-RV64 %s

#include <riscv_vector.h>

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2
// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vlmul_ext_v_f16mf4_f16mf2(vfloat16mf4_t op1) {
  return __riscv_vlmul_ext_v_f16mf4_f16mf2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vlmul_ext_v_f16mf4_f16m1(vfloat16mf4_t op1) {
  return __riscv_vlmul_ext_v_f16mf4_f16m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2
// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vlmul_ext_v_f16mf4_f16m2(vfloat16mf4_t op1) {
  return __riscv_vlmul_ext_v_f16mf4_f16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vlmul_ext_v_f16mf4_f16m4(vfloat16mf4_t op1) {
  return __riscv_vlmul_ext_v_f16mf4_f16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8
// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) {
  return __riscv_vlmul_ext_v_f16mf4_f16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vlmul_ext_v_f16mf2_f16m1(vfloat16mf2_t op1) {
  return __riscv_vlmul_ext_v_f16mf2_f16m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vlmul_ext_v_f16mf2_f16m2(vfloat16mf2_t op1) {
  return __riscv_vlmul_ext_v_f16mf2_f16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4
// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vlmul_ext_v_f16mf2_f16m4(vfloat16mf2_t op1) {
  return __riscv_vlmul_ext_v_f16mf2_f16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8
// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vlmul_ext_v_f16mf2_f16m8(vfloat16mf2_t op1) {
  return __riscv_vlmul_ext_v_f16mf2_f16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2
// CHECK-RV64-SAME: (<vscale x 4 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vlmul_ext_v_f16m1_f16m2(vfloat16m1_t op1) {
  return __riscv_vlmul_ext_v_f16m1_f16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4
// CHECK-RV64-SAME: (<vscale x 4 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vlmul_ext_v_f16m1_f16m4(vfloat16m1_t op1) {
  return __riscv_vlmul_ext_v_f16m1_f16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8
// CHECK-RV64-SAME: (<vscale x 4 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vlmul_ext_v_f16m1_f16m8(vfloat16m1_t op1) {
  return __riscv_vlmul_ext_v_f16m1_f16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4
// CHECK-RV64-SAME: (<vscale x 8 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vlmul_ext_v_f16m2_f16m4(vfloat16m2_t op1) {
  return __riscv_vlmul_ext_v_f16m2_f16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8
// CHECK-RV64-SAME: (<vscale x 8 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vlmul_ext_v_f16m2_f16m8(vfloat16m2_t op1) {
  return __riscv_vlmul_ext_v_f16m2_f16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m4_f16m8
// CHECK-RV64-SAME: (<vscale x 16 x half> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vlmul_ext_v_f16m4_f16m8(vfloat16m4_t op1) {
  return __riscv_vlmul_ext_v_f16m4_f16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vlmul_ext_v_f32mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1) {
  return __riscv_vlmul_ext_v_f32mf2_f32m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vlmul_ext_v_f32mf2_f32m2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) {
  return __riscv_vlmul_ext_v_f32mf2_f32m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlmul_ext_v_f32mf2_f32m4
// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv1f32(<vscale x 8 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1) {
  return __riscv_vlmul_ext_v_f32mf2_f32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32mf2_f32m8
// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv1f32(<vscale x 16 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1) {
  return __riscv_vlmul_ext_v_f32mf2_f32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vlmul_ext_v_f32m1_f32m2
// CHECK-RV64-SAME: (<vscale x 2 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1) {
  return __riscv_vlmul_ext_v_f32m1_f32m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlmul_ext_v_f32m1_f32m4
// CHECK-RV64-SAME: (<vscale x 2 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> poison, <vscale x 2 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1) {
  return __riscv_vlmul_ext_v_f32m1_f32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32m1_f32m8
// CHECK-RV64-SAME: (<vscale x 2 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> poison, <vscale x 2 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1) {
  return __riscv_vlmul_ext_v_f32m1_f32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlmul_ext_v_f32m2_f32m4
// CHECK-RV64-SAME: (<vscale x 4 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> poison, <vscale x 4 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1) {
  return __riscv_vlmul_ext_v_f32m2_f32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32m2_f32m8
// CHECK-RV64-SAME: (<vscale x 4 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> poison, <vscale x 4 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1) {
  return __riscv_vlmul_ext_v_f32m2_f32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32m4_f32m8
// CHECK-RV64-SAME: (<vscale x 8 x float> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> poison, <vscale x 8 x float> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1) {
  return __riscv_vlmul_ext_v_f32m4_f32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vlmul_ext_v_f64m1_f64m2
// CHECK-RV64-SAME: (<vscale x 1 x double> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> poison, <vscale x 1 x double> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1) {
  return __riscv_vlmul_ext_v_f64m1_f64m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vlmul_ext_v_f64m1_f64m4
// CHECK-RV64-SAME: (<vscale x 1 x double> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> poison, <vscale x 1 x double> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1) {
  return __riscv_vlmul_ext_v_f64m1_f64m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vlmul_ext_v_f64m1_f64m8
// CHECK-RV64-SAME: (<vscale x 1 x double> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> poison, <vscale x 1 x double> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1) {
  return __riscv_vlmul_ext_v_f64m1_f64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vlmul_ext_v_f64m2_f64m4
// CHECK-RV64-SAME: (<vscale x 2 x double> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> poison, <vscale x 2 x double> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1) {
  return __riscv_vlmul_ext_v_f64m2_f64m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vlmul_ext_v_f64m2_f64m8
// CHECK-RV64-SAME: (<vscale x 2 x double> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> poison, <vscale x 2 x double> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1) {
  return __riscv_vlmul_ext_v_f64m2_f64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vlmul_ext_v_f64m4_f64m8
// CHECK-RV64-SAME: (<vscale x 4 x double> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> poison, <vscale x 4 x double> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1) {
  return __riscv_vlmul_ext_v_f64m4_f64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vlmul_ext_v_i8mf8_i8mf4
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
  return __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_i8mf8_i8mf2
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1) {
  return __riscv_vlmul_ext_v_i8mf8_i8mf2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_i8mf8_i8m1
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1) {
  return __riscv_vlmul_ext_v_i8mf8_i8m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8mf8_i8m2
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1) {
  return __riscv_vlmul_ext_v_i8mf8_i8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8mf8_i8m4
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1) {
  return __riscv_vlmul_ext_v_i8mf8_i8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8mf8_i8m8
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1) {
  return __riscv_vlmul_ext_v_i8mf8_i8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_i8mf4_i8mf2
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1) {
  return __riscv_vlmul_ext_v_i8mf4_i8mf2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_i8mf4_i8m1
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1) {
  return __riscv_vlmul_ext_v_i8mf4_i8m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8mf4_i8m2
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1) {
  return __riscv_vlmul_ext_v_i8mf4_i8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8mf4_i8m4
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1) {
  return __riscv_vlmul_ext_v_i8mf4_i8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8mf4_i8m8
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1) {
  return __riscv_vlmul_ext_v_i8mf4_i8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_i8mf2_i8m1
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1) {
  return __riscv_vlmul_ext_v_i8mf2_i8m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8mf2_i8m2
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1) {
  return __riscv_vlmul_ext_v_i8mf2_i8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8mf2_i8m4
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1) {
  return __riscv_vlmul_ext_v_i8mf2_i8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8mf2_i8m8
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1) {
  return __riscv_vlmul_ext_v_i8mf2_i8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8m1_i8m2
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1) {
  return __riscv_vlmul_ext_v_i8m1_i8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8m1_i8m4
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1) {
  return __riscv_vlmul_ext_v_i8m1_i8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8m1_i8m8
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1) {
  return __riscv_vlmul_ext_v_i8m1_i8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8m2_i8m4
// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1) {
  return __riscv_vlmul_ext_v_i8m2_i8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8m2_i8m8
// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1) {
  return __riscv_vlmul_ext_v_i8m2_i8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8m4_i8m8
// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1) {
  return __riscv_vlmul_ext_v_i8m4_i8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vlmul_ext_v_i16mf4_i16mf2
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1) {
  return __riscv_vlmul_ext_v_i16mf4_i16mf2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_i16mf4_i16m1
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1) {
  return __riscv_vlmul_ext_v_i16mf4_i16m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_i16mf4_i16m2
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1) {
  return __riscv_vlmul_ext_v_i16mf4_i16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16mf4_i16m4
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1) {
  return __riscv_vlmul_ext_v_i16mf4_i16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16mf4_i16m8
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
  return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_i16mf2_i16m1
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1) {
  return __riscv_vlmul_ext_v_i16mf2_i16m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_i16mf2_i16m2
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1) {
  return __riscv_vlmul_ext_v_i16mf2_i16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16mf2_i16m4
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1) {
  return __riscv_vlmul_ext_v_i16mf2_i16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16mf2_i16m8
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1) {
  return __riscv_vlmul_ext_v_i16mf2_i16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_i16m1_i16m2
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1) {
  return __riscv_vlmul_ext_v_i16m1_i16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16m1_i16m4
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1) {
  return __riscv_vlmul_ext_v_i16m1_i16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16m1_i16m8
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1) {
  return __riscv_vlmul_ext_v_i16m1_i16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16m2_i16m4
// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1) {
  return __riscv_vlmul_ext_v_i16m2_i16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16m2_i16m8
// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1) {
  return __riscv_vlmul_ext_v_i16m2_i16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16m4_i16m8
// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1) {
  return __riscv_vlmul_ext_v_i16m4_i16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlmul_ext_v_i32mf2_i32m1
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1) {
  return __riscv_vlmul_ext_v_i32mf2_i32m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_i32mf2_i32m2
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1) {
  return __riscv_vlmul_ext_v_i32mf2_i32m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_i32mf2_i32m4
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1) {
  return __riscv_vlmul_ext_v_i32mf2_i32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32mf2_i32m8
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1) {
  return __riscv_vlmul_ext_v_i32mf2_i32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_i32m1_i32m2
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1) {
  return __riscv_vlmul_ext_v_i32m1_i32m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_i32m1_i32m4
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1) {
  return __riscv_vlmul_ext_v_i32m1_i32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32m1_i32m8
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1) {
  return __riscv_vlmul_ext_v_i32m1_i32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_i32m2_i32m4
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1) {
  return __riscv_vlmul_ext_v_i32m2_i32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32m2_i32m8
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1) {
  return __riscv_vlmul_ext_v_i32m2_i32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32m4_i32m8
// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1) {
  return __riscv_vlmul_ext_v_i32m4_i32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vlmul_ext_v_i64m1_i64m2
// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1) {
  return __riscv_vlmul_ext_v_i64m1_i64m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_i64m1_i64m4
// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1) {
  return __riscv_vlmul_ext_v_i64m1_i64m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_i64m1_i64m8
// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1) {
  return __riscv_vlmul_ext_v_i64m1_i64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_i64m2_i64m4
// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1) {
  return __riscv_vlmul_ext_v_i64m2_i64m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_i64m2_i64m8
// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
  return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_i64m4_i64m8
// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1) {
  return __riscv_vlmul_ext_v_i64m4_i64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vlmul_ext_v_u8mf8_u8mf4
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1) {
  return __riscv_vlmul_ext_v_u8mf8_u8mf4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_u8mf8_u8mf2
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1) {
  return __riscv_vlmul_ext_v_u8mf8_u8mf2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_u8mf8_u8m1
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1) {
  return __riscv_vlmul_ext_v_u8mf8_u8m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8mf8_u8m2
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1) {
  return __riscv_vlmul_ext_v_u8mf8_u8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8mf8_u8m4
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1) {
  return __riscv_vlmul_ext_v_u8mf8_u8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8mf8_u8m8
// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1) {
  return __riscv_vlmul_ext_v_u8mf8_u8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_u8mf4_u8mf2
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1) {
  return __riscv_vlmul_ext_v_u8mf4_u8mf2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_u8mf4_u8m1
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1) {
  return __riscv_vlmul_ext_v_u8mf4_u8m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8mf4_u8m2
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1) {
  return __riscv_vlmul_ext_v_u8mf4_u8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8mf4_u8m4
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1) {
  return __riscv_vlmul_ext_v_u8mf4_u8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8mf4_u8m8
// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1) {
  return __riscv_vlmul_ext_v_u8mf4_u8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_u8mf2_u8m1
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1) {
  return __riscv_vlmul_ext_v_u8mf2_u8m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8mf2_u8m2
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1) {
  return __riscv_vlmul_ext_v_u8mf2_u8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8mf2_u8m4
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1) {
  return __riscv_vlmul_ext_v_u8mf2_u8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8mf2_u8m8
// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1) {
  return __riscv_vlmul_ext_v_u8mf2_u8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8m1_u8m2
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1) {
  return __riscv_vlmul_ext_v_u8m1_u8m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8m1_u8m4
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1) {
  return __riscv_vlmul_ext_v_u8m1_u8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8m1_u8m8
// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1) {
  return __riscv_vlmul_ext_v_u8m1_u8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8m2_u8m4
// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1) {
  return __riscv_vlmul_ext_v_u8m2_u8m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8m2_u8m8
// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1) {
  return __riscv_vlmul_ext_v_u8m2_u8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8m4_u8m8
// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1) {
  return __riscv_vlmul_ext_v_u8m4_u8m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vlmul_ext_v_u16mf4_u16mf2
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1) {
  return __riscv_vlmul_ext_v_u16mf4_u16mf2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_u16mf4_u16m1
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1) {
  return __riscv_vlmul_ext_v_u16mf4_u16m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_u16mf4_u16m2
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1) {
  return __riscv_vlmul_ext_v_u16mf4_u16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16mf4_u16m4
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1) {
  return __riscv_vlmul_ext_v_u16mf4_u16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16mf4_u16m8
// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1) {
  return __riscv_vlmul_ext_v_u16mf4_u16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_u16mf2_u16m1
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1) {
  return __riscv_vlmul_ext_v_u16mf2_u16m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_u16mf2_u16m2
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1) {
  return __riscv_vlmul_ext_v_u16mf2_u16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16mf2_u16m4
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1) {
  return __riscv_vlmul_ext_v_u16mf2_u16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16mf2_u16m8
// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1) {
  return __riscv_vlmul_ext_v_u16mf2_u16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_u16m1_u16m2
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1) {
  return __riscv_vlmul_ext_v_u16m1_u16m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16m1_u16m4
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1) {
  return __riscv_vlmul_ext_v_u16m1_u16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16m1_u16m8
// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1) {
  return __riscv_vlmul_ext_v_u16m1_u16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16m2_u16m4
// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1) {
  return __riscv_vlmul_ext_v_u16m2_u16m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16m2_u16m8
// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1) {
  return __riscv_vlmul_ext_v_u16m2_u16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16m4_u16m8
// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1) {
  return __riscv_vlmul_ext_v_u16m4_u16m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlmul_ext_v_u32mf2_u32m1
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1) {
  return __riscv_vlmul_ext_v_u32mf2_u32m1(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_u32mf2_u32m2
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1) {
  return __riscv_vlmul_ext_v_u32mf2_u32m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_u32mf2_u32m4
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1) {
  return __riscv_vlmul_ext_v_u32mf2_u32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32mf2_u32m8
// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1) {
  return __riscv_vlmul_ext_v_u32mf2_u32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_u32m1_u32m2
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1) {
  return __riscv_vlmul_ext_v_u32m1_u32m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_u32m1_u32m4
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1) {
  return __riscv_vlmul_ext_v_u32m1_u32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32m1_u32m8
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1) {
  return __riscv_vlmul_ext_v_u32m1_u32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_u32m2_u32m4
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1) {
  return __riscv_vlmul_ext_v_u32m2_u32m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32m2_u32m8
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1) {
  return __riscv_vlmul_ext_v_u32m2_u32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32m4_u32m8
// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1) {
  return __riscv_vlmul_ext_v_u32m4_u32m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vlmul_ext_v_u64m1_u64m2
// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1) {
  return __riscv_vlmul_ext_v_u64m1_u64m2(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_u64m1_u64m4
// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1) {
  return __riscv_vlmul_ext_v_u64m1_u64m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_u64m1_u64m8
// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1) {
  return __riscv_vlmul_ext_v_u64m1_u64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_u64m2_u64m4
// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1) {
  return __riscv_vlmul_ext_v_u64m2_u64m4(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_u64m2_u64m8
// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1) {
  return __riscv_vlmul_ext_v_u64m2_u64m8(op1);
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_u64m4_u64m8
// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT:  entry:
// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 0)
// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1) {
  return __riscv_vlmul_ext_v_u64m4_u64m8(op1);
}