llvm/lld/ELF/Arch/RISCV.cpp

//===- RISCV.cpp ----------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "InputFiles.h"
#include "OutputSections.h"
#include "Symbols.h"
#include "SyntheticSections.h"
#include "Target.h"
#include "llvm/Support/ELFAttributes.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/RISCVAttributeParser.h"
#include "llvm/Support/RISCVAttributes.h"
#include "llvm/Support/TimeProfiler.h"
#include "llvm/TargetParser/RISCVISAInfo.h"

usingnamespacellvm;
usingnamespacellvm::object;
usingnamespacellvm::support::endian;
usingnamespacellvm::ELF;
usingnamespacelld;
usingnamespacelld::elf;

namespace {

class RISCV final : public TargetInfo { … };

} // end anonymous namespace

// These are internal relocation numbers for GP relaxation. They aren't part
// of the psABI spec.
#define INTERNAL_R_RISCV_GPREL_I …
#define INTERNAL_R_RISCV_GPREL_S …

const uint64_t dtpOffset = …;

namespace {
enum Op { … };

enum Reg { … };
} // namespace

static uint32_t hi20(uint32_t val) { … }
static uint32_t lo12(uint32_t val) { … }

static uint32_t itype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t imm) { … }
static uint32_t rtype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t rs2) { … }
static uint32_t utype(uint32_t op, uint32_t rd, uint32_t imm) { … }

// Extract bits v[begin:end], where range is inclusive, and begin must be < 63.
static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) { … }

static uint32_t setLO12_I(uint32_t insn, uint32_t imm) { … }
static uint32_t setLO12_S(uint32_t insn, uint32_t imm) { … }

RISCV::RISCV(Ctx &ctx) : … { … }

static uint32_t getEFlags(InputFile *f) { … }

uint32_t RISCV::calcEFlags() const { … }

int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const { … }

void RISCV::writeGotHeader(uint8_t *buf) const { … }

void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const { … }

void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const { … }

void RISCV::writePltHeader(uint8_t *buf) const { … }

void RISCV::writePlt(uint8_t *buf, const Symbol &sym,
                     uint64_t pltEntryAddr) const { … }

RelType RISCV::getDynRel(RelType type) const { … }

RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
                          const uint8_t *loc) const { … }

void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { … }

static bool relaxable(ArrayRef<Relocation> relocs, size_t i) { … }

static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) { … }

static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) { … }

void RISCV::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const { … }

void elf::initSymbolAnchors() { … }

// Relax R_RISCV_CALL/R_RISCV_CALL_PLT auipc+jalr to c.j, c.jal, or jal.
static void relaxCall(const InputSection &sec, size_t i, uint64_t loc,
                      Relocation &r, uint32_t &remove) { … }

// Relax local-exec TLS when hi20 is zero.
static void relaxTlsLe(const InputSection &sec, size_t i, uint64_t loc,
                       Relocation &r, uint32_t &remove) { … }

static void relaxHi20Lo12(const InputSection &sec, size_t i, uint64_t loc,
                          Relocation &r, uint32_t &remove) { … }

static bool relax(InputSection &sec) { … }

// When relaxing just R_RISCV_ALIGN, relocDeltas is usually changed only once in
// the absence of a linker script. For call and load/store R_RISCV_RELAX, code
// shrinkage may reduce displacement and make more relocations eligible for
// relaxation. Code shrinkage may increase displacement to a call/load/store
// target at a higher fixed address, invalidating an earlier relaxation. Any
// change in section sizes can have cascading effect and require another
// relaxation pass.
bool RISCV::relaxOnce(int pass) const { … }

void RISCV::finalizeRelax(int passes) const { … }

namespace {
// Representation of the merged .riscv.attributes input sections. The psABI
// specifies merge policy for attributes. E.g. if we link an object without an
// extension with an object with the extension, the output Tag_RISCV_arch shall
// contain the extension. Some tools like objdump parse .riscv.attributes and
// disabling some instructions if the first Tag_RISCV_arch does not contain an
// extension.
class RISCVAttributesSection final : public SyntheticSection { … };
} // namespace

static void mergeArch(RISCVISAUtils::OrderedExtensionMap &mergedExts,
                      unsigned &mergedXlen, const InputSectionBase *sec,
                      StringRef s) { … }

static void mergeAtomic(DenseMap<unsigned, unsigned>::iterator it,
                        const InputSectionBase *oldSection,
                        const InputSectionBase *newSection,
                        RISCVAttrs::RISCVAtomicAbiTag oldTag,
                        RISCVAttrs::RISCVAtomicAbiTag newTag) { … }

static RISCVAttributesSection *
mergeAttributesSection(const SmallVector<InputSectionBase *, 0> &sections) { … }

void RISCVAttributesSection::writeTo(Ctx &ctx, uint8_t *buf) { … }

void elf::mergeRISCVAttributesSections(Ctx &) { … }

TargetInfo *elf::getRISCVTargetInfo(Ctx &ctx) { … }