#include "ARMBaseInstrInfo.h"
#include "ARMFeatures.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "MCTargetDesc/ARMInstPrinter.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "TargetInfo/ARMTargetInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
#include "llvm/MC/MCParser/MCAsmParserUtils.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ARMBuildAttributes.h"
#include "llvm/Support/ARMEHABI.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include "llvm/TargetParser/TargetParser.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <optional>
#include <string>
#include <utility>
#include <vector>
#define DEBUG_TYPE …
usingnamespacellvm;
namespace {
class ARMOperand;
enum class ImplicitItModeTy { … };
static cl::opt<ImplicitItModeTy> ImplicitItMode(
"arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
cl::desc("Allow conditional instructions outside of an IT block"),
cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
"Accept in both ISAs, emit implicit ITs in Thumb"),
clEnumValN(ImplicitItModeTy::Never, "never",
"Warn in ARM, reject in Thumb"),
clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
"Accept in ARM, reject in Thumb"),
clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
"Warn in ARM, emit implicit ITs in Thumb")));
static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
cl::init(false));
enum VectorLaneTy { … };
static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) { … }
class UnwindContext { … };
class ARMMnemonicSets { … };
ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) { … }
class ARMAsmParser : public MCTargetAsmParser { … };
class ARMOperand : public MCParsedAsmOperand { … };
}
void ARMOperand::print(raw_ostream &OS) const { … }
static MCRegister MatchRegisterName(StringRef Name);
static bool isDataTypeToken(StringRef Tok) { … }
static unsigned getMnemonicOpsEndInd(const OperandVector &Operands) { … }
bool ARMAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) { … }
ParseStatus ARMAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) { … }
MCRegister ARMAsmParser::tryParseRegister(bool AllowOutOfBoundReg) { … }
std::optional<ARM_AM::ShiftOpc> ARMAsmParser::tryParseShiftToken() { … }
int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { … }
bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { … }
static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { … }
ParseStatus ARMAsmParser::parseITCondCode(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { … }
static unsigned getNextRegister(unsigned Reg) { … }
static bool
insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, MCRegister>> &Regs,
unsigned Enc, MCRegister Reg) { … }
bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
bool AllowRAAC, bool AllowOutOfBoundReg) { … }
ParseStatus ARMAsmParser::parseVectorLane(VectorLaneTy &LaneKind,
unsigned &Index, SMLoc &EndLoc) { … }
ParseStatus ARMAsmParser::parseVectorList(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { … }
ParseStatus
ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { … }
ParseStatus
ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parsePKHImm(OperandVector &Operands,
ARM_AM::ShiftOpc Op, int Low, int High) { … }
ParseStatus ARMAsmParser::parseSetEndImm(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseShifterImm(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseRotImm(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseModImm(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseBitfield(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { … }
ParseStatus ARMAsmParser::parseAM3Offset(OperandVector &Operands) { … }
unsigned findCondCodeInd(const OperandVector &Operands,
unsigned MnemonicOpsEndInd) { … }
unsigned findCCOutInd(const OperandVector &Operands,
unsigned MnemonicOpsEndInd) { … }
void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
const OperandVector &Operands) { … }
void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
const OperandVector &Operands) { … }
void ARMAsmParser::cvtMVEVMOVQtoDReg(
MCInst &Inst, const OperandVector &Operands) { … }
bool ARMAsmParser::parseMemory(OperandVector &Operands) { … }
bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
unsigned &Amount) { … }
ParseStatus ARMAsmParser::parseFPImm(OperandVector &Operands) { … }
bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { … }
bool ARMAsmParser::parseImmExpr(int64_t &Out) { … }
bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { … }
StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
ARMCC::CondCodes &PredicationCode,
ARMVCC::VPTCodes &VPTPredicationCode,
bool &CarrySetting,
unsigned &ProcessorIMod,
StringRef &ITMask) { … }
void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
StringRef ExtraToken,
StringRef FullInst,
bool &CanAcceptCarrySet,
bool &CanAcceptPredicationCode,
bool &CanAcceptVPTPredicationCode) { … }
bool operandsContainWide(OperandVector &Operands, unsigned MnemonicOpsEndInd) { … }
void ARMAsmParser::tryConvertingToTwoOperandForm(
StringRef Mnemonic, ARMCC::CondCodes PredicationCode, bool CarrySetting,
OperandVector &Operands, unsigned MnemonicOpsEndInd) { … }
static bool isThumbI8Relocation(MCParsedAsmOperand &MCOp) { … }
bool ARMAsmParser::shouldOmitVectorPredicateOperand(
StringRef Mnemonic, OperandVector &Operands, unsigned MnemonicOpsEndInd) { … }
static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { … }
static void applyMnemonicAliases(StringRef &Mnemonic,
const FeatureBitset &Features,
unsigned VariantID);
void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
OperandVector &Operands,
unsigned MnemonicOpsEndInd) { … }
bool ARMAsmParser::CDEConvertDualRegOperand(StringRef Mnemonic,
OperandVector &Operands,
unsigned MnemonicOpsEndInd) { … }
void removeCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) { … }
void removeCCOut(OperandVector &Operands, unsigned &MnemonicOpsEndInd) { … }
void removeVPTCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) { … }
bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) { … }
static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
unsigned Reg, unsigned HiReg,
bool &containsReg) { … }
static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) { … }
static bool instIsBreakpoint(const MCInst &Inst) { … }
unsigned getRegListInd(const OperandVector &Operands,
unsigned MnemonicOpsEndInd) { … }
bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
const OperandVector &Operands,
unsigned MnemonicOpsEndInd,
unsigned ListIndex, bool IsARPop) { … }
bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
const OperandVector &Operands,
unsigned MnemonicOpsEndInd,
unsigned ListIndex) { … }
bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
bool Load, bool ARMMode, bool Writeback,
unsigned MnemonicOpsEndInd) { … }
static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) { … }
static bool isVectorPredicable(const MCInstrDesc &MCID) { … }
static bool isARMMCExpr(MCParsedAsmOperand &MCOp) { … }
bool ARMAsmParser::validateInstruction(MCInst &Inst,
const OperandVector &Operands,
unsigned MnemonicOpsEndInd) { … }
static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { … }
static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { … }
bool ARMAsmParser::processInstruction(MCInst &Inst,
const OperandVector &Operands,
unsigned MnemonicOpsEndInd,
MCStreamer &Out) { … }
unsigned
ARMAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
const OperandVector &Operands) { … }
unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { … }
namespace llvm {
template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) { … }
}
bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const { … }
unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
SmallVectorImpl<NearMissInfo> &NearMisses,
bool MatchingInlineAsm,
bool &EmitInITBlock,
MCStreamer &Out) { … }
static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
unsigned VariantID = 0);
static const char *getSubtargetFeatureName(uint64_t Val);
bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) { … }
bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { … }
bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { … }
bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveARM(SMLoc L) { … }
MCSymbolRefExpr::VariantKind
ARMAsmParser::getVariantKindForName(StringRef Name) const { … }
void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc) { … }
void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { … }
bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveCode(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { … }
bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { … }
void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) { … }
bool ARMAsmParser::parseDirectiveArch(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { … }
bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { … }
bool ARMAsmParser::parseDirectivePad(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { … }
bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { … }
bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveEven(SMLoc L) { … }
bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveSEHAllocStack(SMLoc L, bool Wide) { … }
bool ARMAsmParser::parseDirectiveSEHSaveRegs(SMLoc L, bool Wide) { … }
bool ARMAsmParser::parseDirectiveSEHSaveSP(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveSEHSaveFRegs(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveSEHSaveLR(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveSEHPrologEnd(SMLoc L, bool Fragment) { … }
bool ARMAsmParser::parseDirectiveSEHNop(SMLoc L, bool Wide) { … }
bool ARMAsmParser::parseDirectiveSEHEpilogStart(SMLoc L, bool Condition) { … }
bool ARMAsmParser::parseDirectiveSEHEpilogEnd(SMLoc L) { … }
bool ARMAsmParser::parseDirectiveSEHCustom(SMLoc L) { … }
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmParser() { … }
#define GET_REGISTER_MATCHER
#define GET_SUBTARGET_FEATURE_NAME
#define GET_MATCHER_IMPLEMENTATION
#define GET_MNEMONIC_SPELL_CHECKER
#include "ARMGenAsmMatcher.inc"
const char *
ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) { … }
void
ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
SmallVectorImpl<NearMissMessage> &NearMissesOut,
SMLoc IDLoc, OperandVector &Operands) { … }
void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
SMLoc IDLoc, OperandVector &Operands) { … }
bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) { … }
bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { … }
unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
unsigned Kind) { … }
bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
StringRef ExtraToken) { … }
std::unique_ptr<ARMOperand> ARMAsmParser::defaultCondCodeOp() { … }
std::unique_ptr<ARMOperand> ARMAsmParser::defaultCCOutOp() { … }
std::unique_ptr<ARMOperand> ARMAsmParser::defaultVPTPredOp() { … }